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参数资料
| 型号： | 5962-8876101EA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 1.5 A SWITCHING REGULATOR, 100 kHz SWITCHING FREQ-MAX, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 9/12页 |
| 文件大小： | 332K |
| 代理商： | 5962-8876101EA |
Functional Description
SWITCHING FREQUENCY CONTROL
The LM78S40 is a variable frequency, variable duty cycle
device. The initial switching frequency is set by the timing
capacitor. (Oscillator frequency is set by a single external
capacitor and may be varied over a range of 100 Hz to
100 kHz). The initial duty cycle is 6:1. This switching fre-
quency and duty cycle can be modified by two
mechanisms — the current limit circuitry (I
pk sense) and the
comparator.
The comparator modifies the OFF time. When the output
voltage is correct, the comparator output is in the HIGH
state and has no effect on the circuit operation. If the out-
put voltage is too high then the comparator output goes
LOW. In the LOW state the comparator inhibits the turn-on
of the output stage switching transistors. As long as the
comparator is LOW the system is in OFF time. As the out-
put current rises the OFF time decreases. As the output
current nears its maximum the OFF time approaches its
minimum value. The comparator can inhibit several ON
cycles, one ON cycle or any portion of an ON cycle. Once
the ON cycle has begun the comparator cannot inhibit un-
til the beginning of the next ON cycle.
The current limit modifies the ON time. The current limit is
activated when a 300 mV potential appears between lead
13 (V
CC) and lead 14 (Ipk). This potential is intended to re-
sult when designed for peak current flows through R
SC.
When the peak current is reached the current limit is
turned on. The current limit circuitry provides for a quick
end to ON time and the immediate start of OFF time.
Generally the oscillator is free running but the current limit
action tends to reset the timing cycle.
Increasing load results in more current limited ON time
and less OFF time. The switching frequency increases
with load current.
USING THE INTERNAL REFERENCE, DIODE, AND
SWITCH
The internal 1.245V reference (pin 8) must be bypassed,
with 0.1 F directly to the ground pin (pin 11) of the
LM78S40, to assure its stability.
V
FD is the forward voltage drop across the internal power
diode. It is listed on the data sheet as 1.25V typical, 1.5V
maximum. If an external diode is used, then its own for-
ward voltage drop must be used for V
FD.
V
SAT is the voltage across the switch element (output tran-
sistors Q1 and Q2) when the switch is closed or ON. This
is listed on the data sheet as Output Saturation Voltage.
“Output saturation voltage 1” is defined as the switching
element voltage for Q2 and Q1 in the Darlington configu-
ration with collectors tied together. This applies to
Figure
1, the step down mode.
“Output saturation voltage 2” is the switching element volt-
age for Q1 only when used as a transistor switch. This ap-
plies to
Figure 2, the step up mode.
For the inverting mode,
Figure 3, the saturation voltage of
the external transistor should be used for V
SAT.
Typical Applications
Characteristic
Condition
Typical
Value
Output Voltage
I
O = 200 mA
10V
Line Regulation
20V
≤ V
I ≤ 30V
1.5 mV
Load Regulation
5.0 mA
≤ I
O
3.0 mV
I
O ≤ 300 mA
Max Output Current
V
O = 9.5V
500 mA
Output Ripple
I
O = 200 mA
50 mV
Efficiency
I
O = 200 mA
74%
Standby Current
I
O = 200 mA
2.8 mA
Note 7: For IO ≥ 200 mA use external diode to limit on-chip power
dissipation.
DS010057-3
FIGURE 1. Typical Step-Down Regulator and
Operational Performance (T
A = 25C)
www.national.com
6
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