参数资料
型号: 5962-8959826MYA
厂商: MICROSS COMPONENTS
元件分类: SRAM
英文描述: 128K X 8 STANDARD SRAM, 55 ns, DSO32
封装: SOJ-32
文件页数: 1/17页
文件大小: 137K
代理商: 5962-8959826MYA
SRAM
MT5C1009
MT5C1009
Rev. 6.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
Austin Semiconductor, Inc.
FEATURES
Access Times: 12, 15, 20, 25, 35, 45, 55 and 70 ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
OPTIONS
MARKING
Timing
12ns access
-12 (IT only)
15ns access
-15
20ns access
-20
25ns access
-25
35ns access
-35
45ns access
-45
55ns access
-55*
70ns access
-70*
Package(s)
Ceramic DIP (400 mil)
C
No. 111
Ceramic DIP (600 mil)
CW
No. 112
Ceramic LCC
EC
No. 207
Ceramic LCC
ECA
No. 208
Ceramic Flatpack
F
No. 303
Ceramic SOJ
DCJ
No. 501
Ceramic SOJ
SOJ
No. 507
2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-89598
MIL-STD-883
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE\
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE\
A2
10
23
A10
A1
11
22
CE\
A0
12
21
DQ8
DQ1
13
20
DQ7
DQ2
14
19
DQ6
DQ3
15
18
DQ5
VSS
16
17
DQ4
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE\
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE\
A2
10
23
A10
A1
11
22
CE\
A0
12
21
DQ8
DQ1
13
20
DQ7
DQ2
14
19
DQ6
DQ3
15
18
DQ5
VSS
16
17
DQ4
NC
1
32 VCC
A16
2
31 A15
A14
3
30 CE2
A12
4
29 WE\
A7
5
28 A13
A6
6
27 A8
A5
7
26 A9
A4
8
25 A11
A3
9
24 OE\
A2 10
23 A10
A1 11
22 CE\
A0 12
21 DQ8
DQ1 13
20 DQ7
DQ2 14
19 DQ6
DQ3 15
18 DQ5
VSS 16
17 DQ4
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
32-Pin Flat Pack (F)
32-Pin LCC (ECA)
GENERAL DESCRIPTION
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design flexibility in high-speed memory
applications, this device offers chip enable (CE\) and output
enable (OE\) features. These enhancements can place the out-
puts in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ and OE\ go LOW.
The devices offer a reduced power standby mode when dis-
abled, allowing system designs to achieve low standby power
requirements.
The “L” version offers a 2V data retention mode, re-
ducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
For more products and information
please visit our web site at
www.austinsemiconductor.com
4 3 2 1 32 31 30
A12
A14
A10
NC
V
CC
A15
CE2
14 15 16 17 18 19 20
DQ2
DQ3
V
SS
DQ4
DQ5
DQ6
DQ7
5
6
7
8
9
10
11
12
13
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
29
28
27
26
25
24
23
22
21
WE
A13
A8
A9
A11
OE
A10
CE1
DQ8
\
6
NC
相关PDF资料
PDF描述
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