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参数资料
| 型号： | 5962-9168902VYA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSHLESS DC MOTOR CONTROLLER, CDIP28 |
| 封装： | HERMETIC SEALED, CERAMIC, DIP-28 |
| 文件页数： | 21/21页 |
| 文件大小： | 298K |
| 代理商： | 5962-9168902VYA |
On
T
ime
0.001
CT – mF
0.01
0.1
1 ms
10 ms
100 ms
10 ms
1 ms
100 ms
RT – 10 k
RT – 30 k
RT – 100 k
RT – 500 k
0.001
0.01
0.1
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
Oscillator
Frequency
COSC (mF)
ROSC – 10 k
ROSC – 100 k
SLUSAG8A
– SEPTEMBER 2011 – REVISED SEPTEMBER 2011
Terminal Functions (continued)
TERMINAL
DESCRIPTION
NAME
NO.
Any time that VCC drops below threshold or the sensed current exceeds the over-current
threshold, the soft-start latch is set. When set, it turns on a transistor that pulls down on
SSTART. Normally, a capacitor is connected to this pin, and the transistor will completely
discharge the capacitor. A comparator senses when the NPN transistor has completely
discharged the capacitor, and allows the soft-start latch to clear when the fault is removed.
When the fault is removed, the soft-start capacitor charges from the on-chip current source.
SSTART clamps the output of the error amplifier, not allowing the error amplifier output
SSTART
24
voltage to exceed SSTART regardless of input. The ramp on RC-OSC can be applied to
PWM In and compared to E/A OUT. With SSTART discharged below 0.2 V and the ramp
minimum being approximately 1.0 V, the PWM comparator keeps the PWM latch cleared and
the outputs off. As SSTART rises, the PWM comparator begins to duty-cycle modulate the
PWM latch until the error amplifier inputs overcome the clamp. This provides for a safe and
orderly motor start-up from an off or fault condition. A 51-k
resister is added between VREF
and SSTART to ensure switching.
Any change in the H1, H2, or H3 inputs loads data from these inputs into the position sensor
latches. At the same time data is loaded, a fixed-width 5-V pulse is triggered on TACH-OUT.
The average value of the voltage on TACH-OUT is directly proportional to speed, so this
output can be used as a true tachometer for speed feedback with an external filter or
TACH-OUT
20
averaging circuit which usually consists of a resistor and capacitor.
Whenever TACH-OUT is high, the position latches are inhibited, such that during the noisiest
part of the commutation cycle, additional commutations are not possible. Although this
effectively sets a maximum rotational speed, the maximum speed can be set above the
highest expected speed, preventing false commutation and chatter.
This device operates with supplies between 10 V and 18 V. Under-voltage lockout keeps all
outputs off below 7.5 V, insuring that the output transistors never turn on until full drive
VCC
19
capability is available. Bypass VCC to ground with an 0.1-
μF ceramic capacitor. Using a
10-
μF electrolytic bypass capacitor as well can be beneficial in applications with high supply
impedance.
This pin provides regulated 5 V for driving Hall-effect devices and speed control circuitry.
VREF reaches 5 V before VCC enables, ensuring that Hall-effect devices powered from
VREF
2
VREF becomes active before the UC1625 drives any output. For proper performance VREF
should be bypassed with at least a 0.1-
μF capacitor to ground.
TYPICAL CHARACTERISTICS
Oscillator Frequency
Tachometer on Time
vs
COSC and ROSC
RT and CT
Figure 2.
Figure 3.
Copyright
2011, Texas Instruments Incorporated
9
Product Folder Link(s) :UC1625-SP
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