- 您现在的位置：买卖IC网 > PDF目录67338 > 5962-9475502MPX (ANALOG DEVICES INC) 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8 PDF资料下载
参数资料
| 型号： | 5962-9475502MPX |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8 |
| 封装： | GLASS SEALED, CERDIP-8 |
| 文件页数： | 13/14页 |
| 文件大小： | 349K |
| 代理商： | 5962-9475502MPX |
AD7893
REV. E
–8–
This scheme limits the throughput rate to 12
s minimum; how-
ever, depending on the response time of the microprocessor to
the interrupt signal and the time taken by the processor to read
the data, this may be the fastest the system could have operated.
In any case, the CONVST signal does not have to have a 50:50
duty cycle. This can be tailored to optimize the throughput rate
of the part for a given system.
Alternatively, the CONVST signal can be used as a normal narrow
pulse width. The rising edge of CONVST can be used as an active
high or rising edge-triggered interrupt. A software delay of 6
s can
then be implemented before data is read from the part.
Serial Interface
The serial interface to the AD7893 consists of just two wires, a
serial clock input (SCLK) and the serial data output (SDATA).
This allows for an easy to use interface to most microcontrollers,
DSP processors and shift registers.
Figure 5 shows the timing diagram for the read operation to the
AD7893. The serial clock input (SCLK) provides the clock
source for the serial interface. Serial data is clocked out from the
SDATA line on the rising edge of this clock and is valid on the
falling edge of SCLK. Sixteen clock pulses must be provided to
the part to access to full conversion result. The AD7893 pro-
vides four leading zeros followed by the 12-bit conversion result
starting with the MSB (DB11). The last data bit to be clocked
out on the final rising clock edge is the LSB (DB0). On the six-
teenth falling edge of SCLK, the SDATA line is disabled (three-
stated). After this last bit has been clocked out, the SCLK input
should return low and remain low until the next serial data read
operation. If there are extra clock pulses after the sixteenth
clock, the AD7893 will start over again with outputting data
from its output register, and the data bus will no longer be
three-stated even when the clock stops. Provided that the serial
clock has stopped before the next falling edge of CONVST, the
AD7893 will continue to operate correctly with the output shift
register being reset on the falling edge of CONVST; however,
the SCLK line must be low when CONVST goes low in order
to reset the output shift register correctly.
The serial clock input does not have to be continuous during the
serial read operation. The sixteen bits of data (four leading zeros
and 12 bit conversion result) can be read from the AD7893 in a
number of bytes; however, the SCLR input must remain low be-
tween the two bytes.
Normally, the output register is updated at the end of conver-
sion. If a serial read from the output register is in progress when
conversion is complete; however, the updating of the output
register is deferred. In this case, the output register is updated
when the serial read is completed. If the serial read has not been
completed before the next falling edge of CONVST, the output
register will be updated on the falling edge of CONVST, and
the output shift register count is reset. In applications where the
data read has been started and not completed before the falling
edge of CONVST, the user must provide a CONVST pulse
width of greater than 1.5
s to ensure correct setup of the AD7893
before the next conversion is initiated. In applications where the
output update takes place either at the end of conversion or at
the end of a serial read that is completed 1.5
s before the rising
edge of CONVST, the normal pulse width of 50 ns minimum
applies to CONVST.
CONVST
SCLK
CONVERSION IS INITIATED
AND TRACK/HOLD GOES
INTO HOLD
CONVST INDICATES
TO P THAT
CONVERSION IS
COMPLETE
tCONVERT
SERIAL READ
OPERATION
P INT SERVICE
OR POLLING
ROUTINE
600ns MIN
READ OPERATION
SHOULD END 600ns
PRIOR TO NEXT
RISING EDGE OF
CONVST
Figure 4. CONVST Used as Status Signal
SDATA (O)
SCLK (I)
FOUR LEADING ZEROS
DB11
DB10
THREE-STATE
DB0
t5
t4
t3
t2
Figure 5. Data Read Operation
相关PDF资料 |
PDF描述 |
|---|---|
| 5962-9555601Q2A | SPECIALTY ANALOG CIRCUIT, CQCC20 |
| 5962-9555601QPA | SPECIALTY ANALOG CIRCUIT, CDIP8 |
| TLE2425CD | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| TLE2425CPSR | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| TLE2425MDR | SPECIALTY ANALOG CIRCUIT, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 5962-9475601MPA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 5962-9475701HXA | 功能描述:模数转换器 - ADC Analog to Digital Converter RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| 5962-9475701HXC | 功能描述:模数转换器 - ADC Analog to Digital Converter RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| 5962-9475901MYC | 制造商:Rochester Electronics LLC 功能描述:10BIT 40 MSPS A/D IC IC - Bulk |
| 5962-9476101MXC | 功能描述:CPLD - 复杂可编程逻辑器件 ISPLSI 102460LH/883 SMD Version RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
发布紧急采购，3分钟左右您将得到回复。