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参数资料
| 型号： | 5962-9961002HXX |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | DUAL 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封装： | CERAMIC, LCC-68 |
| 文件页数： | 3/20页 |
| 文件大小： | 1702K |
| 代理商： | 5962-9961002HXX |
REV. A
AD10200
–11–
LAYOUT INFORMATION
The schematic of the evaluation board (Figure 8) represents
a typical implementation of the AD10200. The pinout of the
AD10200 is very straightforward and facilitates ease of use and
the implementation of high frequency/high resolution design
practices. It is recommended that high quality ceramic chip
capacitors be used to decouple each supply pin to ground directly
at the device. All capacitors can be standard high quality ceramic
chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high-slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the ADC through a resistor network to eliminate
the need to externally isolate the device from the receiving gate.
Figure 8. Evaluation Board Mechanical Layout
EVALUATION BOARD
The AD10200 evaluation board (Figure 9) is designed to
provide optimal performance for evaluation of the AD10200
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10200. The board requires an analog input signal, encode
clock and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD10200. The digital outputs of the
AD10200 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
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