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参数资料
| 型号： | 5962F0153701QXA |
| 元件分类： | 多路复用及模拟开关 |
| 英文描述： | QUAD 2-CHANNEL, CROSS POINT SWITCH, DFP64 |
| 封装： | DFP-64 |
| 文件页数： | 14/15页 |
| 文件大小： | 108K |
| 代理商： | 5962F0153701QXA |
8
AC SWITCHING CHARACTERISTICS
(VDD = +3.3V + 0.3V, TA = -55 °C to +125 °C)
Notes:
1. Guaranteed by characterization.
2. TSET and THOLD time specify that data must be in a stable state before and after SEL transition.
3. Guaranteed by design.
4. Max tPZH and tPZL = 4.5ns when EN or ENCL = VDD on another channel.
SYMBOL
PARAMETER
Conditions
MIN
MAX
UNIT
tSET
1, 2
Input to SEL Setup Time (Figure 3 & 4)
RL=35Ω, CL=10pf
1.6
ns
tHOLD
1,2
Input to SEL Hold Time (Figure 3 & 4)
RL=35Ω, CL=10pf
1.5
ns
tSWITCH
1
SEL to Switched Output (Figure 3 & 4)
RL=35Ω, CL=10pf
3.0
ns
tPHZ
1
Disable Time (Active to Tri-State) High to Z
(Figure 5 & 8)
RL=35Ω, CL=10pf
4.5
ns
tPLZ
1
Disable Time (Active to Tri-State) Low to Z
(Figure 5 & 8)
RL=35Ω, CL=10pf
4.5
ns
tPZH
1,4
Enable Time (Tri-State to Active) Z to High
(Figure 5 & 8)
RL=35Ω, CL=10pf
EN on other channels = GND
11.0
ns
tPZL
1,4
Enable Time (Tri-State to Active) Z to Low
(Figure 5 & 8)
RL=35Ω, CL=10pf
EN on other channels = GND
11.0
ns
tLHT
3
Output Low-to-High Transition Time, 20% to 80%
(Figure 5 & 6)
RL=35Ω, CL=10pf
600
ps
tHLT
3
Output High-to-Low Transition Time, 80% to 20%
(Figure 5 & 6)
RL=35Ω, CL=10pf
600
ps
tPLHD
Propagation Low to High Delay (Figure 5 & 7)
RL=35Ω, CL=10pf
3.5
ns
TPHLD
Propagation High to Low Delay (Figure 5 & 7)
RL=35Ω, CL=10pf
3.5
ns
TSKEW
Pulse Skew TPHLD - TPLHD (Figure 5 & 7)
900
ps
TCCS
Output Channel-to-Channel Skew (Figure 5 & 9)
500
ps
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