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参数资料
| 型号： | 5962R0722601VZA |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 12-BIT DAC, CDSO10 |
| 封装： | CERAMIC, SOIC-10 |
| 文件页数： | 7/22页 |
| 文件大小： | 493K |
| 代理商： | 5962R0722601VZA |
1.0 Functional Description
1.1 DAC SECTION
The DAC121S101 is fabricated on a CMOS process with an
architecture that consists of switches and a resistor string that
are followed by an output buffer. The power supply serves as
the reference voltage. The input coding is straight binary with
an ideal output voltage of:
V
OUT = VA x (D / 4096)
where D is the decimal equivalent of the binary code that is
loaded into the DAC register and can take on any value be-
tween 0 and 4095.
1.2 RESISTOR STRING
The simplified resistor string is shown in Figure 3. Conceptu-
ally, this string consists of 4096 equal valued resistors with a
switch at each junction of two resistors, plus a switch to
ground. The code loaded into the DAC register determines
which switch is closed, connecting the proper node to the
amplifier. This configuration guarantees that the DAC is
monotonic.
30018007
FIGURE 3. DAC Resistor String
1.3 OUTPUT AMPLIFIER
The output buffer amplifier is a rail-to-rail type, providing an
output voltage range of 0V to V
A. All amplifiers, even rail-to-
rail types, exhibit a loss of linearity as the output approaches
the supply rails (0V and V
A, in this case). For this reason,
linearity is specified over less than the full output range of the
DAC. The output capabilities of the amplifier are described in
the Electrical Tables.
1.4 SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and
MICROWIRE, as well as most DSPs. See the Timing Diagram
for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once
SYNC is low, the data on the D
IN line is clocked into the 16-
bit serial input register on the falling edges of SCLK. On the
16th falling clock edge, the last data bit is clocked in and the
programmed function (a change in the mode of operation and/
or a change in the DAC register contents) is executed. At this
point the SYNC line may be kept low or brought high. In either
case, it must be brought high for the minimum specified time
before the next write sequence as a falling edge of SYNC can
initiate the next write cycle.
Since the SYNC and D
IN buffers draw more current when they
are high, they should be idled low between write sequences
to minimize power consumption.
1.5 INPUT SHIFT REGISTER
The input shift register, Figure 4, has sixteen bits. The first
two bits are "don't cares" and are followed by two bits that
determine the mode of operation (normal mode or one of
three power-down modes). The contents of the serial input
register are transferred to the DAC register on the sixteenth
falling edge of SCLK. See Timing Diagram, Figure 2.
30018008
FIGURE 4. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling
edges of SCLK and the DAC is updated on the 16th SCLK
falling edge. However, if SYNC is brought high before the 16th
falling edge, the shift register is reset and the write sequence
is invalid. The DAC register is not updated and there is no
change in the mode of operation or in the output voltage.
1.6 POWER-ON RESET
The power-on reset circuit controls the output voltage during
power-up. Upon application of power the DAC register is filled
with zeros and the output voltage is 0 Volts and remains there
until a valid write sequence is made to the DAC.
1.7 POWER-DOWN MODES
The DAC121S101 has four modes of operation. These
modes are set with two bits (DB13 and DB12) in the control
register.
TABLE 1. Modes of Operation
DB13
DB12
Operating Mode
0
Normal Operation
0
1
Power-Down with 5k
to GND
1
0
Power-Down with 100k
to GND
1
Power-Down with Hi-Z
When both DB13 and DB12 are 0, the device operates nor-
mally. For the other three possible combinations of these bits
the supply current drops to its power-down level and the out-
put is pulled down with either a 5k
or a 100k resistor, or is
in a high impedance state, as described in Table 1.
The bias generator, output amplifier, the resistor string and
other linear circuitry are all shut down in any of the power-
down modes. Minimum power consumption is achieved in the
power-down mode with SCLK disabled and SYNC and D
IN
idled low.
15
www.national.com
DAC121S101QML
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