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参数资料
| 型号： | 5962R0922501QXC |
| 厂商： | INTERSIL CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, CQFP48 |
| 封装： | ROHS COMPLIANT, CQFP-48 |
| 文件页数： | 16/16页 |
| 文件大小： | 592K |
| 代理商： | 5962R0922501QXC |
ISL70001SRH
9
FN6947.1
May 23, 2011
Functional Description
The ISL70001SRH is a monolithic, fixed frequency, current-mode
synchronous buck regulator with user configurable power blocks.
Two ISL70001SRH devices can be used to provide a total DC/DC
solution for FPGAs, CPLDs, DSPs and CPUs.
Power Blocks
The power output stage of the regulator consists of six 1A
capable power blocks that are paralleled to provide full 6A
output current capability. The block diagram in Figure 3 shows a
top level view of the individual power blocks.
Each power block has a power supply input pin, PVINx, a phase
output pin, LXx, and a power supply ground pin, PGNDx. All PVINx
pins must be connected to a common power supply rail and all
PGNDx pins must be connected to a common ground. LXx pins
should be connected to the output inductor based on the
required load current, but must include the LX4 pin. For example,
if 3A of output current is needed, any three LXx pins can be
connected to the inductor as long as one of them is the LX4 pin.
The unused LXx pins should be left unconnected. Connecting all
six LXx pins to the output inductor provides a maximum 6A of
output current. See the “Typical Application Schematic” on
page 5 for pin connection guidance.
A scaled pilot device associated with each power block provides
current feedback. Power block 4 contains the master pilot device
and this is why it must be connected to the output inductor.
Main Control Loop
During normal operation, the internal top power switch is turned
on at the beginning of each clock cycle. Current in the output
inductor ramps up until the current comparator trips and turns
off the top power MOSFET. The bottom power MOSFET turns on
and the inductor current ramps down for the rest of the cycle.
The current comparator compares the output current at the
ripple current peak to a current pilot. The error amplifier monitors
VOUT and compares it with an internal reference voltage. The
output voltage of the error amplifier drives a proportional current
to the pilot. If VOUT is low, the current level of the pilot is
increased and the trip off current level of the output is increased.
The increased output current raises VOUT until it is in agreement
with the reference voltage.
Output Voltage Selection
The output voltage of the ISL70001SRH can be adjusted using
selected as 1k
Ω to mitigate SEE. RT should be shunted by a
4.7nF ceramic capacitor, CC, to mitigate SEE and to improve loop
stability margins. The REF pin should be bypassed to AGND with
a 220nF ceramic capacitor to mitigate SEE. It should be noted
that no current (sourcing or sinking) is available from the REF pin.
configure the output voltage from 0.8V to 85% of the input
voltage.
Switching Frequency/Synchronization
The ISL70001SRH features an internal oscillator running at a
fixed frequency of 1MHz ±15% over recommended operating
conditions. The regulator can be configured to run from the
internal oscillator or can be synchronized to another
ISL70001SRH or an SEE hardened external clock with a
frequency range of 1MHz ±20%.
To run the regulator from the internal oscillator, connect the M/S
pin to DVDD. In this case, the output of the internal oscillator
appears on the SYNC pin. To synchronize the regulator to the
SYNC output of another ISL70001SRH regulator or to an SEE
hardened external clock, connect the M/S pin to DGND. In this
case, the SYNC pin is an input that accepts an external
synchronizing signal. When synchronizing multiple devices, Slave
regulators are synchronized 180° out-of-phase with respect to
the SYNC output of a Master regulator or to an external clock.
Operation Initialization
The ISL70001SRH initializes based on the state of the power-on
reset (POR) monitor of the PVINx inputs and the state of the EN
input. Successful initialization prompts a soft-start interval, and
the regulator begins slowly ramping the output voltage. Once the
commanded output voltage is within the proper window of
operation, the power-good signal changes state from low to high,
indicating proper regulator operation.
Power-On Reset
The POR circuitry prevents the controller from attempting to
soft-start before sufficient bias is present at the PVINx pins.
POWER BLOCK 6
PGND6
POWER BLOCK 5
POWER BLOCK 4
POWER BLOCK 1
POWER BLOCK 2
POWER BLOCK 3
PVIN6
PGND5
PVIN5
PGND4
PVIN4
PGND1
PVIN1
PGND2
PVIN2
PGND3
PVIN3
FIGURE 3. POWER BLOCK DIAGRAM
LX2
LX1
LX3
LX6
LX5
LX4
FIGURE 4. OUTPUT VOLTAGE SELECTION
FB
COUT
LOUT
VOUT
LXx
RT
RB
VREF
ERROR
AMPLIFIER
REF
CREF
-
+
CC
VREF = 0.6V
CREF = 220nF
RT = 1k
CC = 4.7nF
RB
RT
VREF
VOUT VREF
–
--------------------------------
=
(EQ. 3)
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