参数资料
型号: 5P49EE802NDGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 17/26页
文件大小: 0K
描述: IC CLOCK GENERATOR 28QFN
标准包装: 75
系列: VersaClock™
类型: 时钟发生器
PLL: 带旁路
输入: LVTTL,晶体
输出: LVCMOS,LVTTL
电路数: 1
比率 - 输入:输出: 2:7
差分 - 输入:输出: 无/是
频率 - 最大: 120MHz
除法器/乘法器: 是/无
电源电压: 1.71 V ~ 1.89 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-VFQFN 裸露焊盘
供应商设备封装: 28-VFQFPN(4x4)
包装: 管件
其它名称: 800-2523
IDT5P49EE802
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
24
IDT5P49EE802
REV M 072512
Package Outline and Package Dimensions (28-pin 4mm x 4mm QFN)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“G” after the two-letter pacakage code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Millimeters
Symbol
Min
Max
A0.80
1.00
A1
0
0.05
A3
0.20 Reference
b0.15
0.25
e
0.40 BASIC
N28
ND
7
NE
7
D x E BASIC
4.00 x 4.00
D2
2.50
2.70
E2
2.50
2.70
L0.30
0.50
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
5P49EE802NDGI
See page 23
Tray
28-pin VFQFPN
-40 to +85
° C
5P49EE802NDGI8
See page 23
Tape and Reel
28-pin VFQFPN
-40 to +85
° C
Sawn
Singulation
1
2
N
E
D
Index Area
Top View
Seating Plane
A3
A1
C
A
L
E2
2
D2
2
e
C
0.08
(Ref)
N
D & NE
Odd
(Ref)
N
D & NE
Even
(N
D-1)x
(Ref)
e
N
1
2
b
Thermal Base
EP – Exposed thermal pad
should be externally
connected to ground.
(Typ)
If N
D & NE
are Even
(N
E-1)x
(Ref)
e
2
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