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参数资料
| 型号： | 702075 |
| 厂商： | Spectrum Digital Inc |
| 文件页数： | 20/92页 |
| 文件大小： | 0K |
| 描述： | PLATFORM DEV DGTL VID FOR DM6437 |
| 标准包装： | 1 |
| 系列： | DaVinci™ |
| 类型： | DSP：视频 |
| 适用于相关产品： | TMS320DM64x |
| 所含物品： | 评估板、电源、缆线、软件和说明文档 |
| 配用： | WM2582-ND - EVALDI EARBUDS TYPE Y |
| 相关产品： | 296-34537-5-ND - IC DGTL MEDIA PROCESSOR 361NFBGA TMS320DM6437ZWTL-ND - IC DGTL MEDIA PROCESSOR 361NFBGA TMS320DM6437ZWT7-ND - IC DGTL MEDIA PROCESSOR 361NFBGA TMS320DM6437ZDUQ6-ND - IC DGTL MEDIA PROCESSOR 376-BGA TMS320DM6437ZDUL-ND - IC DGTL MEDIA PROCESSOR 376-BGA TMS320DM6437ZDU7-ND - IC DGTL MEDIA PROCESSOR 376-BGA TMS320DM6435ZWTQ6-ND - IC DGTL MEDIA PROCESSOR 361NFBGA TMS320DM6435ZWTL-ND - IC DGTL MEDIA PROCESSOR 361NFBGA TMS320DM6435ZWT7-ND - IC DGTL MEDIA PROCESSOR 361NFBGA TMS320DM6435ZDUQ6-ND - IC DGTL MEDIA PROCESSOR 376-BGA 更多... |
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Spectrum Digital, Inc
2.4 AIC33 Interface
The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output of
audio signals. The codec samples analog signals on the microphone or line inputs and
converts them into digital data so it can be processed by the DSP. When the DSP is
finished with the data it uses the codec to convert the samples back into analog signals
on the line output so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. The I 2 C bus
is used as the unidirectional control channel. The control channel is generally only used
when configuring the codec, it is typically idle when audio data is being transmitted,
The default configuration is to use the McBSP is used as the bi-directional data
channel. However, optionally the McASP can be used to drive the data channel. Data
channel selection is controller via an on board I 2 C expander. All audio data flows
through the data channel. Many data formats are supported based on the three
variables of sample width, clock signal source and serial data format. The EVM
examples generally use a 16-bit sample width with the codec in master mode so it
generates the frame sync and bit clocks at the correct sample rate without effort on the
DSP side.
The codec has a programmable clock from a PLL1705 PLL device. The default system
clock is 18.432 Mhz. The internal sample rate generate subdivides the 18.432 MHz
clock to generate common frequencies such as 48KHz and 8KHz. The sample rate is
set by a codec register. The figure below shows the codec interface on the DM6437
EVM.
AIC33 Codec
I 2 C
MIC IN
SCL
Control
SCL
SDA
I 2 C Format
SDA
Control Registers
LINE IN
Digital
Analog
LINE OUT
McASP or McBSP
AXR[0]
AXR[1]
ACLKR
ACLKX
AFSR
DX
DR
CLKR
CLKX
FSR
I2S Format
DOUT
DIN
BCLK
WCLK
ADC
DAC
MIC IN
LINE IN
LINE OUT
AFSX
FSX
HP OUT
HP OUT
Figure 2-2, DM6437 EVM CODEC INTERFACE
2-4
DM6437 EVM Technical Reference
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