参数资料
型号: 70V05L35PF8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: SRAM
英文描述: 8K X 8 DUAL-PORT SRAM, 35 ns, PQFP64
封装: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64
文件页数: 1/22页
文件大小: 159K
代理商: 70V05L35PF8
2001 Integrated Device Technology, Inc.
DECEMBER 2001
DSC 2941/7
1
IDT70V05S/L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V05S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V05L
Active: 380mW (typ.)
Standby: 660
W (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
WL
CEL
OEL
BUSYL
A12L
A0L
2942 drw 01
I/O0L-I/O7L
CEL
OEL
R/
WL
SEML
INTL
M/
S
BUSYR
I/O0R-I/O7R
A12R
A0R
SEMR
INTR
CER
OER
(2)
(1,2)
(2)
R/
WR
CER
OER
13
R/WR
,
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70V05L55J8 功能描述:静态随机存取存储器 8K x 8 3.3v Dual- Port Ram RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray