- 您现在的位置：买卖IC网 > PDF目录299201 > 7207L35J (INTEGRATED DEVICE TECHNOLOGY INC) 32K X 9 OTHER FIFO, 35 ns, PQCC32 PDF资料下载
参数资料
| 型号： | 7207L35J |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 32K X 9 OTHER FIFO, 35 ns, PQCC32 |
| 封装： | PLASTIC, LCC-32 |
| 文件页数： | 11/14页 |
| 文件大小： | 147K |
| 代理商： | 7207L35J |
6
COMMERCIAL,INDUSTRIALANDMILITARY
TEMPERATURERANGES
IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO
2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9
loaded(seeOperatingModes).TheSingleDeviceModeisinitiatedbygrounding
the Expansion In (
XI).
The IDT7203/7204/7205/7206/7207/7208 can be made to retransmit data
when the Retransmit Enable Control (
RT) input is pulsed LOW. A retransmit
operationwillsettheinternalreadpointertothefirstlocationandwillnotaffectthe
writepointer. ThestatusoftheFlagswillchangedependingontherelativelocations
of the read and write pointers. Read Enable (
R) and Write Enable (W) must be
intheHIGHstateduringretransmit. Thisfeatureisusefulwhenlessthan2,048/
4,096/8,192/16,384/32,768/65,536writesareperformedbetweenresets. The
retransmitfeatureisnotcompatiblewiththeDepthExpansionMode.
EXPANSION IN (
XI)—Thisinputisadual-purposepin. ExpansionIn(XI)
isgroundedtoindicateanoperationinthesingledevicemode. ExpansionIn(
XI)
isconnectedtoExpansionOut(
XO)ofthepreviousdeviceintheDepthExpansion
or Daisy-Chain Mode.
OUTPUTS:
FULL FLAG
( FF)—TheFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations,whenthedeviceisfull. IfthereadpointerisnotmovedafterReset(
RS),
the Full Flag (
FF) will go LOW after 2,048/4,096/8,192/16,384/32,768/65,536
writes.
EMPTY FLAG (
EF)—TheEmptyFlag(EF)willgoLOW,inhibitingfurther
readoperations,whenthereadpointerisequaltothewritepointer,indicatingthat
thedeviceisempty.
EXPANSIONOUT/HALF-FULLFLAG(
XO/HF)—Thisisadual-purpose
output. Inthesingledevicemode,whenExpansionIn(
XI)isgrounded,thisoutput
actsasanindicationofahalf-fullmemory.
Afterhalfofthememoryisfilled,andatthefallingedgeofthenextwriteoperation,
the Half-Full Flag (
HF)willbesettoLOWandwillremainsetuntilthedifference
betweenthewritepointerandreadpointerislessthanorequaltoonehalfofthe
totalmemoryofthedevice. TheHalf-FullFlag(
HF)isthenresetbytherisingedge
of the read operation.
IntheDepthExpansionMode,ExpansionIn(
XI)isconnectedtoExpansion
Out (
XO) of the previous device. This output acts as a signal to the next device
intheDaisyChainbyprovidingapulsetothenextdevicewhenthepreviousdevice
reaches the last location of memory. There will be an
XOpulsewhentheWrite
pointerreachesthelastlocationofmemory,andanadditional
XOpulsewhenthe
Readpointerreachesthelastlocationofmemory.
DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-bit wide data.
Theseoutputsareinahigh-impedanceconditionwheneverRead(
R)isinaHIGH
state.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0–D8)
— Data inputs for 9-bit wide data.
CONTROLS:
RESET (
RS ) — Reset is accomplished whenever the Reset (RS) input is
takentoaLOWstate. Duringreset,bothinternalreadandwritepointersareset
tothefirstlocation.Aresetisrequiredafterpower-upbeforeawriteoperationcan
take place. Both the Read Enable (
R) and Write Enable (W) inputs must
be in the HIGH state during the window shown in Figure 2 (i.e. tRSS before
the rising edge of
RS) and should not change until tRSR after the rising
edge of
RS.
WRITE ENABLE (
W ) — A write cycle is initiated on the falling edge of this
inputiftheFullFlag(
FF)isnotset.Dataset-upandholdtimesmustbeadhered-
to,withrespecttotherisingedgeoftheWriteEnable(
W).DataisstoredintheRAM
array sequentially and independently of any on-going read operation.
Afterhalfofthememoryisfilled,andatthefallingedgeofthenextwriteoperation,
theHalf-FullFlag(
HF)willbesettoLOW,andwillremainsetuntilthedifference
betweenthewritepointerandreadpointerisless-thanorequaltoone-halfofthe
totalmemoryofthedevice.TheHalf-FullFlag(
HF)isthenresetbytherisingedge
of the read operation.
To prevent data overflow, the Full Flag (
FF)willgoLOWonthefallingedge
ofthelastwritesignal,whichinhibitsfurtherwriteoperations. Uponthecompletion
of a valid read operation, the Full Flag (
FF) will go HIGH after tRFF, allowing a
newvalidwritetobegin.WhentheFIFOisfull,theinternalwritepointerisblocked
from
W, so external changes in Wwill not affect the FIFO when it is full.
READENABLE(
R)—A readcycleisinitiatedonthefallingedgeoftheRead
Enable (
R), provided the Empty Flag (EF) is not set. The data is accessed on
aFirst-In/First-Outbasis,independentofanyongoingwriteoperations. AfterRead
Enable (
R) goes HIGH, the Data Outputs (Q0 through Q8) will return to a high-
impedanceconditionuntilthenextReadoperation. Whenallthedatahasbeen
read from the FIFO, the Empty Flag (
EF) will go LOW, allowing the “final” read
cyclebutinhibitingfurtherreadoperations,withthedataoutputsremaininginahigh-
impedancestate.Onceavalidwriteoperationhasbeenaccomplished,theEmpty
Flag (
EF) will go HIGH after tWEF and a valid Read can then begin. When the
FIFOisempty,theinternalreadpointerisblockedfrom
Rsoexternalchangeswill
not affect the FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
FL/RT ) — This is a dual-purpose input. In
theDepthExpansionMode,thispinisgroundedtoindicatethatitisthefirstdevice
相关PDF资料 |
PDF描述 |
|---|---|
| 7207L50P | 32K X 9 OTHER FIFO, 50 ns, PDIP28 |
| IDT72235LB25J | CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 |
| 72205LB15PFI | 256 X 18 OTHER FIFO, 10 ns, PQFP64 |
| 72205LB25TFI | 256 X 18 OTHER FIFO, 15 ns, PQFP64 |
| 72215LB10TFG8 | 512 X 18 OTHER FIFO, 6.5 ns, PQFP64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 7207L35J8 | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 7207L35P | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 7207L3D9AV2BE2 | 功能描述:拨动开关 Toggle RoHS:否 制造商:C&K Components 触点形式:DPDT 开关功能:ON - ON - ON 电流额定值: 电压额定值 AC:20 V 电压额定值 DC:20 V 功率额定值:0.4 VA 端接类型:V-Bracket 安装风格: 端子密封:Epoxy 触点电镀:Gold 照明:Not Illuminated |
| 7207L3DZ3BE2 | 功能描述:拨动开关 Toggle RoHS:否 制造商:C&K Components 触点形式:DPDT 开关功能:ON - ON - ON 电流额定值: 电压额定值 AC:20 V 电压额定值 DC:20 V 功率额定值:0.4 VA 端接类型:V-Bracket 安装风格: 端子密封:Epoxy 触点电镀:Gold 照明:Not Illuminated |
| 7207L3Y9ZQE2 | 功能描述:拨动开关 Toggle RoHS:否 制造商:C&K Components 触点形式:DPDT 开关功能:ON - ON - ON 电流额定值: 电压额定值 AC:20 V 电压额定值 DC:20 V 功率额定值:0.4 VA 端接类型:V-Bracket 安装风格: 端子密封:Epoxy 触点电镀:Gold 照明:Not Illuminated |
发布紧急采购，3分钟左右您将得到回复。