参数资料
型号: 723631L15PF9
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: FIFO
英文描述: 512 X 36 OTHER FIFO, 11 ns, PQFP120
封装: TQFP-120
文件页数: 1/21页
文件大小: 219K
代理商: 723631L15PF9
1
SEPTEMBER 2002
DSC-2023/5
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
CMOS SyncFIFO
512 x 36
1,024 x 36
2,048 x 36
IDT723631
IDT723641
IDT723651
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:
Storage capacity:
IDT723631 - 512 x 36
IDT723641 - 1,024 x 36
IDT723651 - 2,048 x 36
Supports clock frequencies up to 67 MHz
Fast access times of 11ns
Free-running CLKA and CLKB can be asynchronous or coinci-
dent (permits simultaneous reading and writing of data on a
single clock edge)
Clocked FIFO buffering data from Port A to Port B
Synchronous read retransmit capability
Mailbox register in each direction
Programmable Almost-Full and Almost-Empty flags
Microprocessor interface control logic
Input Ready (IR) and Almost-Full (AF) flags synchronized by
CLKA
Output Ready (OR) and Almost-Empty (AE) flags synchronized
by CLKB
Available in 132-pin plastic quad flat package (PQFP) or space-
saving 120-pin thin quad flat package (TQFP)
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT723631/723641/723651 is a monolithic high-speed, low-power,
CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz
and has read access times as fast as 12ns. The 512/1,024/2,048 x 36
dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory
has retransmit capability, which allows previously read data to be ac-
cessed again. The FIFO has flags to indicate empty and full conditions and
two programmable flags (Almost-Full and Almost-Empty) to indicate when a
selected number of words is stored in memory. Communication between
each port may take place with two 36-bit mailbox registers. Each mailbox
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Input
Register
Output
Register
CLKA
CSA
W/
RA
ENA
MBA
Port-A
Control
Logic
Reset
Logic
RST
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
OR
AE
B0 - B35
3023 drw01
Mail 2
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
MBF2
IR
AF
FS0/SD
FS1/
SEN
Flag Offset
Registers
A0 - A35
10
Sync
Retransmit
Logic
RTM
RFM
RAM ARRAY
512 x 36
1,024 x 36
2,048 x 36
36
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