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| 型号： | 73M1903C-EVM |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/23页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 73M1903C WORLDWIDE |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 接口，模拟前端（AFE） |
| 已用 IC / 零件： | * |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | * |
UM_1903C_030
73M1903C Evaluation Board User Manual
2.2
73M1903C Register Map
read or written by a host controller or a DSP using the MAFE interface control frame format.
All registers and their bits are described in detail in the 73M1903C Data Sheet .
Table 1: 73M1903C Register Memory Map
Address Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
0x08
ENFE
SelTX2
TXBST1
TXBST0
TXDIS
RXG1
RXG0
RXGAIN
0x01
0x00
TMEN
DIGLB
ANALB
INTLB
CkoutEn RXPULL
SPOS
HC
0x02
0x03
0xFF
0xFF
GPIO7
DIR7
GPIO 6
DIR6
GPIO 5
DIR5
GPIO 4
DIR4
GPIO 3
DIR3
GPIO 2
DIR2
GPIO 1
DIR1
GPIO 0
DIR0
0x04
0x05
0x00
0x00
reserved
reserved
reserved
reserved
reserved reserved reserved reserved reserved reserved
reserved reserved reserved reserved reserved reserved
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x50
0x00
0x00
0x0A
0x22
0x12
0x00
0xC0
0x00
Rev3
Unused
Pseq7
Prst2
Ichp3
Unused
Nseq7
Xtal1
Frcvco
Rev2
TestPll
Pseq6
Prst1
Ichp2
Ndvsr6
Nseq6
Xtal0
PwdnPLL
Rev1
Tclksel1
Pseq5
Prst0
Ichp1
Ndvsr5
Nseq5
LokdetEn
Lokdet
Rev0
Tclksel0
Pseq4
Pdvsr4
Ichp0
Ndvsr4
Nseq4
ThLk0
Unused
FSBDEn
ATX
Pseq3
Pdvsr3
FL
Ndvsr3
Nseq3
Unused
Unused
Trim(2)
DTX
Pseq2
Pdvsr2
Kvco2
Ndvsr2
Nseq2
Nrst2
Unused
Trim(1)
ARX
Pseq1
Pdvsr1
Kvco1
Ndvsr1
Nseq1
Nrst1
Unused
Trim(0)
DRX
Pseq0
Pdvsr0
Kvco0
Ndvsr0
Nseq0
Nrst0
Unused
2.3
73M1903C System Initialization
The following example shows the sequence to follow to bring the 73M1903C device out of reset and to
start up after power up.
The 73M1903C device does not have a power on reset circuit. For proper operation, a reset
signal must be asserted from the host by pulling the 73M1903C reset pin low for approximately
100 ns or longer after the power is stabilized. The 73M1903C device will be ready to use
within 100 μs after the removal of the reset pulse from the reset pin.
RESET the 73M1903 Device
1.
2.
3.
4.
Power up the system.
Wait for the 3.3 V power to become stable.
Hold the 73M1903C RESET pin low for 100 ns or longer then let it go high.
Wait for 100 μs for the PLL and OSC to be stabilized.
INITIALIZE the 73M1903 Device
There are control operating modes; Hardware Control and Software control. In the Hardware Control
mode, the serial interface will alternate between data frames and control frames. If synchronization is lost
and it is not known whether a data or control frame is being sent, it is necessary to reinitialize the HC
mode. Since there isn’t way to initially tell the difference between whether a control frame or data frame is
being sent, it is necessary to send a reset of this bit in two consecutive frames, and the procedure for this
is as follows:
A. Frame Synchronization
1. Reset the HC bit (Register 0x01 bit 0) in a frame sequence.
Rev. 2.0
9
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