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| 型号： | 73S1209F-EB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/123页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 73S1209F DOC/CD CABLE |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | * |
| 嵌入式： | * |
| 已用 IC / 零件： | * |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | 板，线缆，CD，电源 |
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73S1209F Data Sheet
DS_1209F_004
ATR Timeout Registers (ATRLsB): 0xFE20
0x00, (ATRMsB): 0xFE1F
0x00
Table 104: The ATRLsB Register
MSB
LSB
ATRTO.7
ATRTO.6
ATRTO.5
ATRTO.4
ATRTO.3
ATRTO.1 ATRTO.2 ATRTO.0
Table 105: The ATRMsB Register
MSB
LSB
ATRTO.15 ATRTO.14 ATRTO.13 ATRTO.12 ATRTO.11 ATRTO.10 ATRTO.9 ATRTO.8
These registers (ATRLsB and ATRLsB) form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU
between the leading edge of the first character and leading edge of the last character of the ATR
response. Timer is enabled when the RCVATR is set and starts when leading edge of the first start bit is
received and disabled when the RCVATR is cleared. An ATR timeout is generated if this time is
exceeded.
TS Timeout Register (STSTO): 0xFE21
0x00
Table 106: The STSTO Register
MSB
LSB
TST0.7
TST0.6
TST0.5
TST0.4
TST0.3
TST0.1
TST0.2
TST0.0
The TS timeout is the time in ETU between the de-assertion of smart card reset and the leading edge of
the TS character in the ATR (when DETTS is set). The timer is started when smart card reset is
de-asserted. An ATR timeout is generated if this time is exceeded (MUTE card).
Reset Time Register (RLength): 0xFE22
0x70
MSB
LSB
RLen.7
RLen.6
RLen.5
RLen.4
RLen.3
RLen.1
RLen.2
RLen.0
Table 107: The RLength Register
Time in ETUs that the hardware delays the de-assertion of RST. If set to zero and RSTCRD = 0, the
hardware adds no extra delay and the hardware will release RST after VCCOK is asserted during
power-up. If set to one, it will delay the release of RST by the time in this register. When the firmware
sets the RSTCRD bit, the hardware will assert reset (RST = 0 on pin). When firmware clears the bit, the
hardware will release RST after the delay specified in Rlen. If firmware sets the RSTCRD bit prior to
instructing the power to be applied to the smart card, the hardware will not release RST after power-up
until RLen after the firmware clears the RSTCRD bit. This provides a means to power up the smart card
and hold it in reset until the firmware wants to release the RST to the selected smart card. Works with
the selected smart card interface.
100
Rev. 1.2
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相关代理商/技术参数 |
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|---|---|
| 73S1209F-IM44 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM44 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Eval Bd Doc Cd Cable |
| 73S1209F-IM68 DK | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd |
| 73S1209F-IM68 EB | 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Eval Brd Doc Cd Cable |
| 73S1210F | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Self-Contained Smart Card Reader with PINpad and Power Management |
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