参数资料
型号: 73S8014R-DB
厂商: Maxim Integrated Products
文件页数: 5/24页
文件大小: 0K
描述: BOARD DEMO 73S8010R 20-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *
UM_8014_010
73S8014R/RN/RT 20SO Demo Board User Manual
1.3
Getting Started
The Figure 1.1 shows the basic connections of the Demo Board.
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Power Supplies: Apply 3.3V to pin 10 of J4 and 5V to pin 10 of J2.
Control signals to the device can be connected through J2 and J4 (see Figure 1.1 and the electrical
schematic Figure 4.1)
Setting the clock frequency with an external clock source
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Set JP1 to the SCLK setting
Apply clock source to pin 1 of J2
Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins allows the following:
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CLKDIV1 = CLKDIV2 = 0
73S8014R clock frequency = SCLK/8
73S8014RN/RT clock frequency = SCLK/6
CLKDIV1 = 0, CLKDIV2 =1 clock frequency = SCLK/4 (all)
CLKDIV1 = 1, CLKDIV2 =0 clock frequency = SCLK (all)
CLKDIV1 = CLKDIV2 = 1 clock frequency = SCLK/2 (all)
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Setting the clock frequency using crystal Y1
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Crystal included in the Demo Board is 12MHz (NDS applications can use 27MHz)
Set JP1 to XTAL position
Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins allows the following:
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Rev. 1.0
CLKDIV1 = CLKDIV2 = 0
12MHz XTAL – clock frequency = 1.5MHz
27MHz XTAL – clock frequency = 4.5MHz
CLKDIV1 = 0, CLKDIV2 =1 clock frequency = 3MHz
12MHz XTAL – clock frequency = 3MHz
27MHz XTAL – clock frequency = 6.75MHz
CLKDIV1 = 1, CLKDIV2 = 0 – clock frequency = 12MHz
12MHz XTAL – clock frequency = 12MHz
27MHz XTAL – Illegal setting. Clock is not guaranteed to be stable as the device spec
max CLK frequency is 20MHz.
CLKDIV1 = CLKDIV2 = 1 clock frequency = 6MHz
12MHz XTAL – clock frequency = 6MHz
27MHz XTAL - clock frequency = 13.5MHz
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