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参数资料
| 型号： | 74ACT715DCQR |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, CDIP20 |
| 封装： | CERAMIC, DIP-20 |
| 文件页数： | 11/16页 |
| 文件大小： | 236K |
| 代理商： | 74ACT715DCQR |
Signal Specification (Continued)
TLF10137 – 4
FIGURE 1 Horizontal Waveform Specification
limitation is imposed because during interlace operation this
value is internally divided by 2 in order to generate serration
and equalization pulses at 2 c the horizontal frequency
Horizontal signals will change on the falling edge of the
CLOCK signal Signal specifications are shown below
Horizontal Period (HPER)
e
REG(4) c ckper
Horizontal Blanking Width e REG(3) b 1 c ckper
Horizontal Sync Width
e
REG(2) b REG(1) c ckper
Horizontal Front Porch
e
REG(1) b 1 c ckper
VERTICAL SYNC AND BLANK SPECIFICATION
All vertical signals are defined in terms of number of lines
per frame This is true in both interlaced and noninterlaced
modes of operation Care must be taken to not specify the
Vertical Registers in terms of lines per field Since the first
CLOCK edge CLOCK
1 causes the first falling edge of
the Vertical Blank (first Horizontal Blank) reference pulse
edges referenced to this first edge are n a 1 lines away
where ‘‘n’’ is the width of the timing in question Registers 5
6 and 7 are programmed in this manner Also in the inter-
laced mode vertical timing is based on half-lines Therefore
registers 5 6 and 7 must contain a value twice the total
horizontal (odd and even) plus 1 (as described above) In
non-interlaced mode all vertical timing is based on whole-
lines Register 8 is always based on whole-lines and does
not add 1 for the first clock The vertical counter starts at
the value of 1 and counts until the value of VMAX No re-
strictions exist on the values placed in the vertical registers
Vertical Blank will change on the leading edge of HBLANK
Vertical Sync will change on the leading edge of HSYNC
(See
Figure 2A )
Vertical Frame Period (VPER) e REG(8) c hper
Vertical Field Period (VPERn) e REG(8) c hpern
Vertical Blanking Width e REG(7) b 1 c hpern
Vertical Syncing Width e REG(6) b REG(5) c hpern
Vertical Front Porch e REG(5) b 1 c hpern
where n e 1 for noninterlaced
n e 2 for interlaced
COMPOSITE SYNC AND BLANK SPECIFICATION
Composite Sync and Blank signals are created by logically
ANDing (ORing) the active LOW (HIGH) signals of the cor-
responding vertical and horizontal components of these sig-
nals The Composite Sync signal may also include serration
andor equalization pulses The Serration pulse interval oc-
curs in place of the Vertical Sync interval Equalization puls-
es occur preceding andor following the Serration pulses
The width and location of these pulses can be programmed
through the registers shown below (See
Figure 2B )
Horizontal Equalization PW e REG(9) b REG(1) c ckper
REG 9 e (HFP) a (HEQP)
a
1
Horizontal Serration PW
e
REG(4)n
a
REG(1)
b
REG(10) c ckper
REG 10 e (HFP) a (HPER
2) b (HSERR) a 1
Where n e 1 for noninterlaced single serrationequalization
n e 2 for noninterlaced double
serrationequalization
n e 2 for interlaced operation
4
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| 74ACT715PC | 功能描述:视频 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| 74ACT715PC_Q | 功能描述:视频 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| 74ACT715RPC | 功能描述:视频 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| 74ACT715RSC | 功能描述:视频 IC Prog Vid Sync Gen RoHS:否 制造商:Fairchild Semiconductor 工作电源电压:5 V 电源电流:80 mA 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-28 封装:Reel |
| 74ACT715-RSC | 功能描述:IC GEN PROG VIDEO SYNC 20-SOIC RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
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