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参数资料
| 型号： | 74ACT823SPCX |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | 9-Bit D Flip-Flop |
| 中文描述： | 9位D触发器 |
| 文件页数： | 2/8页 |
| 文件大小： | 158K |
| 代理商： | 74ACT823SPCX |
Functional Description
The ’ACT823 consists of nine D-type edge-triggered flip-
flops. These have TRI-STATE outputs for bus systems or-
ganized with inputs and outputs on opposite sides. The buff-
ered clock (CP) and buffered Output Enable (OE) are com-
mon to all flip-flops. The flip-flops will store the state of their
individual D inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH CP transition. With OE
LOW, the contents of the flip-flops are available at the out-
puts. When OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect
the state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR) and Clock Enable (EN)
pins. These devices are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the EN
is HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Function Table
Inputs
Internal
Output
Function
OE
CLR
EN
CP
D
Q
O
H
H
H
L
H
L
H
H
L
L
X
X
L
L
H
H
H
H
H
H
L
L
X
X
H
H
L
L
L
L
L
L
X
X
X
X
L
L
L
L
L
H
X
X
X
X
L
H
L
H
L
H
L
L
NC
NC
L
H
L
H
Z
Z
Z
L
Z
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
NC
Z
Z
L
H
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance
L
e
LOW-to-HIGH Transition
NC
e
No Change
Logic Diagram
TL/F/9894–5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
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