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参数资料
| 型号： | 74AHC04PWDH |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 通用总线功能 |
| 英文描述： | CERAMIC CHIP/MIL-PRF-55681 |
| 中文描述： | AHC SERIES, HEX 1-INPUT INVERT GATE, PDSO14 |
| 封装： | 4.40 MM, PLASTIC, SOT-402-1, TSSOP-14 |
| 文件页数： | 2/16页 |
| 文件大小： | 73K |
| 代理商： | 74AHC04PWDH |
1999 Sep 27
2
Philips Semiconductors
Product specification
Hex inverter
74AHC04; 74AHCT04
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
Balanced propagation delays
Inputsacceptsvoltageshigherthan
V
CC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125
°
C.
DESCRIPTION
The 74AHC/AHCT04 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT04 provide six
inverting buffers.
FUNCTION TABLE
See note 1.
Note
1.
H = HIGH voltage level;
L = LOW voltage level.
INPUT nA
OUTPUT nY
L
H
H
L
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
PINNING
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation
delay nA to nY
input
capacitance
powerdissipation
capacitance
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
3.0
3.0
ns
C
I
4.0
4.0
pF
C
PD
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
13.5
13.9
pF
PIN
SYMBOL
DESCRIPTION
1, 3, 5, 9, 11 and 13
2, 4, 6, 8, 10 and 12
7
14
1A to 6A
1Y to 6Y
GND
V
CC
data inputs
data outputs
ground (0 V)
DC supply voltage
相关PDF资料 |
PDF描述 |
|---|---|
| 74AHCT04PWDH | CERAMIC CHIP/MIL-PRF-55681 |
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| 74AHC08 | Quad 2-input AND gate |
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