参数资料
型号: 74AHC164
厂商: NXP Semiconductors N.V.
英文描述: 8-bit serial-in/parallel-out shift register
中文描述: 8位serial-in/parallel-out移位寄存器
文件页数: 2/20页
文件大小: 92K
代理商: 74AHC164
2000 Aug 15
2
Philips Semiconductors
Product specification
8-bit serial-in/parallel-out shift register
74AHC164; 74AHCT164
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
40 to +85
°
C and from
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT164 shift registers are high-speed
silicon-gate CMOS devices and are pin compatible with
Low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT164 input signals are 8-bit serial
through one of two inputs (D
sa
or D
sb
); either input can be
used as an active HIGH enable for data entry through the
other input. Both inputs must be connected together or an
unused input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH
transition of the clock (CP) input and enters into Q
0
, which
is a logical AND of the two data inputs (D
sa
, D
sb
) that
existed one set-up time prior to the rising clock edge.
A LOW level on the master reset (MR) input overrides all
other inputs and clears the register asynchronously,
forcing all outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
CP to Q
n
MR to Q
n
input capacitance
maximum clock frequency
power dissipation capacitance
C
L
= 15 pF; V
CC
= 5 V
4.5
4.0
3
175
48
3.4
3.5
3
175
51
ns
ns
pF
MHz
pF
C
I
f
max
C
PD
V
I
= V
CC
or GND
C
L
= 15 pF; V
CC
= 5 V
C
L
= 50 pF; f = 1 MHz; notes 1 and 2
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