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参数资料
| 型号： | 74AHC1G14 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | Inverting Schmitt trigger |
| 中文描述： | 反相施密特触发器 |
| 文件页数： | 2/16页 |
| 文件大小： | 74K |
| 代理商： | 74AHC1G14 |
2002 May 27
2
Philips Semiconductors
Product specification
2-input NAND gate
74AHC1G00; 74AHCT1G00
FEATURES
Symmetrical output impedance
High noise immunity
ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
Low power dissipation
Balanced propagation delays
Very small 5-pin package
Output capability: standard
Specified from
40 to +125
°
C.
DESCRIPTION
The74AHC1G/AHCT1G00isahigh-speedSi-gateCMOS
device.
The 74AHC1G/AHCT1G00 provides the 2-input NAND
function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC1G
AHCT1G
t
PHL
/t
PLH
C
I
C
PD
propagation delay A and B to Y
input capacitance
power dissipation capacitance
C
L
= 15 pF; V
CC
= 5 V
3.5
1.5
17
3.6
1.5
18
ns
pF
pF
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
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