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参数资料
| 型号： | 74AHC573 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple 2-Input Positive-NAND Gates With Open-Drain Outputs 14-SOIC -40 to 85 |
| 中文描述： | 八路D型透明锁存器，三态 |
| 文件页数： | 11/20页 |
| 文件大小： | 91K |
| 代理商： | 74AHC573 |
1999 Sep 27
11
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC573; 74AHCT573
74AHCT573
GND = 0 V; t
r
= t
f
≤
3.0 ns.
Note
1.
Typical values at V
CC
= 5.0 V.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
°
C)
UNIT
WAVEFORMS
C
L
25
40 to +85
40 to +125
MIN.
TYP.
MAX. MIN. MAX.
MIN.
MAX.
V
CC
= 4.5 to 5.5 V;
note 1
t
PHL
/t
PLH
propagation delay
D
n
to Q
n
propagation delay
LE to Q
n
propagation delay
OE to Q
n
propagation delay
OE to Q
n
propagation delay
D
n
to Q
n
propagation delay
LE to Q
n
propagation delay
OE to Q
n
propagation delay
OE to Q
n
enable pulse width
HIGH
set-up time
D
n
to LE
hold time
D
n
to LE
see Figs 6 and 9
15 pF
3.5
5.5
1
6.5
1
7.0
ns
see Figs 7 and 9
3.9
6.0
1
7.0
1
7.5
ns
t
PZH
/t
PZL
see Figs 8 and 9
4.1
6.5
1
7.5
1
8.5
ns
t
PHZ
/t
PLZ
4.5
6.5
1
7.5
1
8.5
ns
t
PHL
/t
PLH
see Figs 6 and 9
50 pF
4.9
7.5
1
8.5
1
9.5
ns
see Figs 7 and 9
5.5
8.5
1
9.5
1
11.0
ns
t
PZH
/t
PZL
see Figs 8 and 9
5.9
8.5
1
10.0
1
11.0
ns
t
PHZ
/t
PLZ
6.4
9.0
1
10.0
1
11.5
ns
t
W
see Figs 7 and 9
5.0
5.0
5.0
ns
t
su
see Fig.9
3.5
3.5
3.5
ns
t
h
1.5
1.5
1.5
ns
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