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参数资料
| 型号： | 74AHCT257 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-SOIC -40 to 85 |
| 中文描述： | 四2输入多路复用器，三态 |
| 文件页数： | 2/20页 |
| 文件大小： | 98K |
| 代理商： | 74AHCT257 |
2000 Apr 03
2
Philips Semiconductors
Product specification
Quad 2-input multiplexer; 3-state
74AHC257;
74AHCT257
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Non-inverting data path
Inputs accept voltages higher than V
CC
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT257 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT257 has four identical 2-input
multiplexers with 3-state outputs, which select 4 bits of
data from two sources and are controlled by a common
data select input (S).
The data inputs from source 0 (1I
0
to 4I
0
) are selected
when input S is LOW and the data inputs from source 1
(1I
1
to 4I
1
) are selected when S is HIGH. Data appears at
the outputs (1Y to 4Y) in true (non-inverting) form from the
selected inputs.
The 74AHC/AHCT257 is the logic implementation of a
4-pole 2-position switch, where the position of the switch is
determined by the logic levels applied to S. The outputs
are forced to a high impedance OFF-state when OE is
HIGH.
If OE is LOW then the logic equations for the outputs are:
1Y = 1I
1
×
S + 1I
0
×
S;
2Y = 2I
1
×
S + 2I
0
×
S;
3Y = 3I
1
×
S + 3I
0
×
S;
4Y = 4I
1
×
S + 4I
0
×
S.
The ‘257’ is identical to the ‘258’ but has non-inverting
(true) outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
nl
0
, nI
1
to nY
S to nY
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 15 pF; V
CC
= 5 V
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
2.9
3.5
3.0
4.0
3.7
5.1
3.0
4.0
ns
ns
pF
pF
C
I
C
O
C
PD
C
L
= 50 pF; f
i
= 1 MHz; notes 1 and 2
4 outputs switching via input S
1 output switching via input I
45
15
51
15
pF
pF
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