参数资料
型号: 74AHCT273PW,118
厂商: NXP Semiconductors
文件页数: 1/13页
文件大小: 0K
描述: IC OCT D FF POS-EDG TRIG 20TSSOP
产品培训模块: Logic Packages
标准包装: 1
系列: 74AHCT
功能: 主复位
类型: D 型总线
输出类型: 非反相
元件数: 1
每个元件的位元数: 8
频率 - 时钟: 50MHz
延迟时间 - 传输: 5.8ns
触发器类型: 正边沿
输出电流高,低: 8mA,8mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 标准包装
其它名称: 568-7613-6
1.
General description
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard
No. 7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type ip-ops with individual D
inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all ip-ops
simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the ip-op.
All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR
input.
The device is useful for applications where only the true output is required and the clock
and master reset are common to all storage elements.
2.
Features
I Balanced propagation delays
I All inputs have Schmitt-trigger actions
I Inputs accept voltages higher than VCC
I Ideal buffer for MOS microcontroller or memory
I Common clock and master reset
I Related product versions:
N 74AHC377; 74AHCT377 for clock enable version
N 74AHC373; 74AHCT373 for transparent latch version
N 74AHC374; 74AHCT374 for 3-state version
I Input levels:
N For 74AHC273: CMOS level
N For 74AHCT273: TTL level
I ESD protection:
N HBM EIA/JESD22-A114E exceeds 2000 V
N MM EIA/JESD22-A115-A exceeds 200 V
N CDM EIA/JESD22-C101C exceeds 1000 V
I Multiple package options
I Specied from 40 °C to +85 °C and from 40 °C to +125 °C
74AHC273; 74AHCT273
Octal D-type ip-op with reset; positive-edge trigger
Rev. 03 — 13 May 2008
Product data sheet
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