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参数资料
型号： 74AHCT373
厂商： NXP Semiconductors N.V.
英文描述： Octal D-type transparent latch; 3-state
中文描述： 八路D型透明锁存器，三态
文件页数： 2/20页
文件大小： 97K
代理商： 74AHCT373
1999 Nov 23
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accepts voltages higher than V
CC
Common 3-state output enable input
Functionally identical to the ‘533’, ‘563’ and ‘573’
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
40 to +85
°
C and
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT373 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT373 are octal D-type transparent
latches featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. A Latch
Enable (LE) input and an Output Enable (OE) input are
common to all latches.
The ‘373’ consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the
D
n
inputs enters the latches. In this condition the latches
are transparent, i.e. a latch output will change state each
time its corresponding D-input changes.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The ‘373’ is functionally identical to the ‘533’, ‘563’ and
‘573’, but the ‘533’ and ‘563’ have inverted outputs and the
‘563’ and ‘573’ have a different pin arrangement.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay
D
n
to Q
n
; LE to Q
n
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 15 pF; V
CC
= 5 V
4.3
4.3
ns
C
I
C
O
C
PD
V
I
= V
CC
or GND
3.0
4.0
10
3.0
4.0
12
pF
pF
pF
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
相关PDF资料
PDF描述
74AHC373 Octal D-type transparent latch; 3-state
74AHC373PWDH Quadruple 2-Input Positive-NOR Gates 14-SO -40 to 85
74AHCT374 Quadruple 2-Input Positive-AND Gates 14-TSSOP -40 to 85
74AHC374PWDH Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374 Quadruple 2-Input Positive-NOR Gates 14-TSSOP -40 to 85
相关代理商/技术参数
参数描述
74AHCT373D 功能描述:闭锁 OCTAL 3-STATE LATCH RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel
74AHCT373D,112 功能描述:闭锁 OCTAL 3-STATE LATCH RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel
74AHCT373D,118 功能描述:闭锁 OCTAL 3-STATE LATCH RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel
74AHCT373D118 制造商:NXP Semiconductors 功能描述:
74AHCT373D-T 功能描述:闭锁 OCTAL 3-STATE LATCH RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel
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