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| 型号： | 74AHCT595 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit serial-in/serial or parallel-out shift register with output latches;3-state(带输出锁存的8位串行输入/串行或并行输出移位寄存器；三态) |
| 中文描述： | 8位serial-in/serial或并行输出的移位寄存器输出锁存器，3态（带输出锁存的8位串行输入/串行或并行输出移位寄存器，三态） |
| 文件页数： | 10/20页 |
| 文件大小： | 103K |
| 代理商： | 74AHCT595 |
2000 Mar 15
10
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
AC CHARACTERISTICS
Type 74AHC595
GND = 0 V; t
r
= t
f
≤
3.0 ns.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
°
C)
UNIT
WAVEFORMS
C
L
25
40 to +85
40 to +125
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
V
CC
= 3.0 to 3.6 V;
note 1
t
PHL
/t
PLH
propagation delay
SH
CP
to Q
7
’
propagation delay
ST
CP
to Q
n
propagation delay
MR to Q
7
’
3-state output enable
time OE to Q
n
3-state output disable
time OE to Q
n
propagation delay
SH
CP
to Q
7
’
propagation delay
ST
CP
to Q
n
propagation delay
MR to Q
7
’
3-state output enable
time OE to Q
n
3-state output disable
time OE to Q
n
shiftclockpulsewidth
HIGH or LOW
storage clock pulse
width HIGH or LOW
master reset pulse
width LOW
set-up time
D
S
to SH
CP
set-up time
SH
CP
to ST
CP
hold time
D
S
to SH
CP
removal time
MR to SH
CP
maximum clock pulse
frequency
SH
CP
or ST
CP
see Figs 7
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 11
and 12
15 pF
5.7
13.0
1.0
15.0
1.0
16.5
ns
5.9
11.9
1.0
13.5
1.0
15.0
ns
t
PHL
5.9
12.8
1.0
13.7
1.0
15.0
ns
t
PZH
/t
PZL
5.6
11.5
1.0
13.5
1.0
15.0
ns
t
PHZ
/t
PLZ
5.4
11.0
1.0
13.0
1.0
14.5
ns
t
PHL
/t
PLH
see Figs 7
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 11
and 12
50 pF
7.7
16.5
1.0
18.5
1.0
20.1
ns
7.7
15.4
1.0
17.0
1.0
18.5
ns
t
PHL
7.4
16.3
1.0
17.2
1.0
18.7
ns
t
PZH
/t
PZL
7.4
15.0
1.0
17.0
1.0
18.5
ns
t
PHZ
/t
PLZ
8.7
15.7
1.0
16.2
1.0
17.5
ns
t
W
see Figs 7
and 12
see Figs 8
and 12
see Figs 10
and 12
see Figs 8
and 12
see Figs 9
and 12
5.0
5.0
5.0
ns
5.0
5.0
5.0
ns
5.0
5.0
5.0
ns
t
su
3.5
3.5
3.5
ns
8.5
8.5
8.5
ns
t
h
1.5
1.5
1.5
ns
t
rem
see Figs 10
and 12
see Figs 7, 8
and 12
3.0
3.0
3.0
ns
f
max
80
125
60
40
MHz
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