参数资料
型号: 74ALVCH16501
厂商: NXP Semiconductors N.V.
英文描述: Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85
中文描述: 18位通用总线收发器,三态
文件页数: 9/13页
文件大小: 86K
代理商: 74ALVCH16501
Philips Semiconductors
Product specification
74ALVCH16501
18-bit universal bus transceiver (3-State)
1998 Sep 29
9
AC WAVEFORMS
V
= 2.3 TO 2.7 V RANGE
1. V
M
= 0.5 V
2. V
X
= V
OL
+ 0.15V
3. V
Y
= V
OH
– 0.15V
4. V
I
= V
CC
5. V
OL
and V
OH
are the typical output voltage drop that occur with
the output load.
V
CC
= 3.0 TO 3.6 V RANGE AND V
CC
= 2.7 V
1. V
M
= 1.5 V
2. V
X
= V
OL
+ 0.3V
3. V
Y
= V
OH
– 0.3V
4. V
I
= 2.7 V
5. V
OL
and V
OH
are the typical output voltage drop that occur with
the output load.
SW00083
An, Bn
INPUT
V
M
t
PHL
t
PLH
V
OL
V
I
V
M
GND
V
OH
Bn, An
OUTPUT
Waveform 1. Input (An, Bn) to output (Bn, An) propagation
delays
SW00092
CP
INPUT
V
M
t
PHL
t
PLH
V
OL
V
I
V
M
GND
V
OH
An, Bn
OUTPUT
t
W
LE
INPUT
1/f
max
Waveform 2. Latch enable input (LE
AB
, LE
BA
) and clock pulse
input (CP
AB
, CP
BA
) to output propagation delays and their
pulse width
t
PLZ
t
PZL
OE
INPUT
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00085
OE
INPUT
V
M
Waveform 3. 3-State enable and disable times
GND
ééééééééé
ééééééééé
t
h
V
M
An, Bn
INPUT
V
M
t
SU
NOTE: The unshaded areas indicate when the input is permitted to change for
predictable output performance.
SW00093
t
SU
V
I
V
I
GND
CP
, LE
XX
INPUT
t
h
Waveform 4. Data set-up and hold times for the An and Bn
inputs to the LE
AB
, LE
BA
, CP
AB
and CP
BA
inputs
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74ALVCH6501 18-bit universal bus transceiver(18位通用总线收发器(三态))
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