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| 型号： | 74ALVCH16543DGG,11 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCVR TRI-ST 16BIT 56SSOP |
| 产品培训模块： | Logic Packages |
| 标准包装： | 2,000 |
| 系列： | 74ALVCH |
| 逻辑类型： | 寄存收发器，非反相 |
| 元件数： | 2 |
| 每个元件的位元数： | 8 |
| 输出电流高，低： | 24mA，24mA |
| 电源电压： | 1.2 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 74ALVCH16543DG-T 74ALVCH16543DG-T-ND 935262544118 |
1999 Nov 23
2
Philips Semiconductors
Product specication
16-bit D-type registered transceiver; 3-state
74ALVCH16543
FEATURES
In accordance with JEDEC standard no 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE flow-through pin-out architecture
16-bit transceiver with D-type latch
Combines 16245 and 16373 type functions in one chip
Back-to-back registers for storage
Output drive capability 50 transmission lines at 85 °C
Separate controls for data flow in each direction
All data inputs have bus hold
3-state non-inverting outputs for bus oriented
applications
Current drive ±24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16543 is a dual octal registered transceiver.
Each section contains two sets of D-type latches for
temporary storage of the data flow in either direction.
Separate latch enable (nLEAB, nLEBA) and output enable
(nOEAB, nOEBA) inputs are provided for each register to
permit independent control in either direction of the data
flow.
The ‘16543’ contains two sections each consisting of two
sets of eight D-type latches with separate inputs and
controls for each set. For data flow from A to B, for
example, the A-to-B enable (nEAB, where n equals 1 or 2)
inputs must be LOW in order to enter data from nA0 to nA7,
or take data from nB0 to nB7, as indicated in the function
table. With nEAB LOW, a LOW signal on the A-to-B latch
enable (nLEAB) input makes the A-to-B latches
transparent; a subsequent LOW-to-HIGH transition of the
nLEAB signal stores the A data into the latches. With nEAB
and nOEAB both LOW, the 3-state B output buffers are
active and display the data present at the output of the
A latches. Similarly, the nEBA, nLEBA and nOEBA signals
control the data flow from B-to-A.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
FUNCTION TABLE
See note 1.
Note
1. XX = AB for A-to-B direction, BA for B-to-A direction;
H = HIGH voltage level; L = LOW voltage level;
h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of nLEAB,nLEBA,nEAB or nEBA;
l = LOW state must be present one set-up time before the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA;
X = don’t care; NC = no change;
↑ = LOW-to-HIGH level transition;
Z = high-impedance OFF-state.
INPUTS
OUTPUTS
STATUS
nOEXX
nEXX
nLEXX
nBn,nAn
H
X
Z
disabled
X
H
X
Z
disabled
L
↑
L
h
Z
disabled and latch
L
↑
Ll
Z
LL
↑
h
H
latch and display
LL
↑
lL
L
H
transparent
LLLL
L
H
X
NC
hold
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| 74ALVCH16543DGGRG4 | 功能描述:总线收发器 16B Reg Xceiver RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74ALVCH16543DGGS | 功能描述:IC TXRX 16BIT TRI-ST 56TSSOP 制造商:nexperia usa inc. 系列:74ALVCH 包装:管件 零件状态:在售 逻辑类型:收发器，非反相 元件数:2 每元件位数:8 输入类型:- 输出类型:推挽式 电流 - 输出高，低:24mA，24mA 电压 - 电源:1.2 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TA） 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商器件封装:56-TSSOP 标准包装:35 |
| 74ALVCH16543DGGY | 功能描述:Transceiver, Non-Inverting 2 Element 8 Bit per Element Push-Pull Output 56-TSSOP 制造商:nxp semiconductors 系列:74ALVCH 包装:带卷（TR） 零件状态:有效 逻辑类型:收发器，非反相 元件数:2 每元件位数:8 输入类型:- 输出类型:推挽式 电流 - 输出高，低:24mA，24mA 电压 - 电源:1.2 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TA） 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商器件封装:56-TSSOP 标准包装:2,000 |
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