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| 型号： | 74ALVCH16652DGG,11 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC 16BIT TXRX/REGISTER 56TSSOP |
| 产品培训模块： | Logic Packages |
| 标准包装： | 2,000 |
| 系列： | 74ALVCH |
| 逻辑类型： | 寄存收发器，非反相 |
| 元件数： | 2 |
| 每个元件的位元数： | 8 |
| 输出电流高，低： | 24mA，24mA |
| 电源电压： | 1.2 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 74ALVCH16652DG-T 74ALVCH16652DG-T-ND 935262799118 |
1999 Nov 23
2
Philips Semiconductors
Product specication
16-bit transceiver/register with dual enable; 3-state
74ALVCH16652
FEATURES
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE flow-through pin-out architecture
Low inductance, multiple supply and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50 transmission lines at 85 °C
Current drive ±24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16652 consists of 16 non-inverting bus
transceiver circuits with 3-state outputs, D-type flip-flops
and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal
storage registers.
Data on the ‘A’ or ‘B’, or both buses, will be stored in the
internal registers, at the appropriate clock inputs
(nCPAB or nCPBA) regardless of the select inputs (nSAB
and nSBA) or output enable (nOEAB and nOEBA) control
inputs.
Depending on the select inputs nSAB and nSBA data can
directly go from input to output (real-time mode) or data
can be controlled by the clock (storage mode), when OE
inputs permit this operating mode.
The output enable inputs nOEAB and nOEBA determine the
operation mode of the transceiver. When nOEAB is LOW,
no data transmission from nBn to nAn is possible and when
nOEBA is HIGH, no data transmission from nBn to nAn is
possible.
When nSAB and nSBA are in the real-time transfer mode, it
is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling nOEAB and
nOEBA. In this configuration each output reinforces its
input.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATA
Ground = 0; Tamb =25 °C; tr =tf = 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
CL = output load capacitance in pF;
fo = output frequency in MHz;
VCC = supply voltage in Volts;
Σ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay nAn,nBn to nBn,nAn
CL = 50 pF; VCC = 3.3 V
2.6
ns
fmax
maximum clock frequency
350
MHz
CI
input capacitance
4.0
pF
CPD
power dissipation capacitance per latch
notes 1 and 2
outputs enabled
22
pF
outputs disabled
4.0
pF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 74ALVCH16652DGGS | 功能描述:IC 16BIT TXRX/REGISTER 56TSSOP 制造商:nexperia usa inc. 系列:74ALVCH 包装:管件 零件状态:在售 逻辑类型:收发器，非反相 元件数:2 每元件位数:8 输入类型:- 输出类型:推挽式 电流 - 输出高，低:24mA，24mA 电压 - 电源:2.3 V ~ 2.7 V，3 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TA） 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商器件封装:56-TSSOP 标准包装:35 |
| 74ALVCH16652DGGY | 功能描述:Transceiver, Non-Inverting 2 Element 8 Bit per Element Push-Pull Output 56-TSSOP 制造商:nxp semiconductors 系列:74ALVCH 包装:带卷（TR） 零件状态:有效 逻辑类型:收发器，非反相 元件数:2 每元件位数:8 输入类型:- 输出类型:推挽式 电流 - 输出高，低:24mA，24mA 电压 - 电源:2.3 V ~ 2.7 V，3 V ~ 3.6 V 工作温度:-40°C ~ 85°C（TA） 安装类型:表面贴装 封装/外壳:56-TFSOP（0.240"，6.10mm 宽） 供应商器件封装:56-TSSOP 标准包装:2,000 |
| 74ALVCH16652DG-T | 功能描述:总线收发器 16-BIT SCVR/REG 3-S RoHS:否 制造商:Fairchild Semiconductor 逻辑类型:CMOS 逻辑系列:74VCX 每芯片的通道数量:16 输入电平:CMOS 输出电平:CMOS 输出类型:3-State 高电平输出电流:- 24 mA 低电平输出电流:24 mA 传播延迟时间:6.2 ns 电源电压-最大:2.7 V, 3.6 V 电源电压-最小:1.65 V, 2.3 V 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74ALVCH16652DL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Dual 8-bit Bus Transceiver |
| 74ALVCH16721APA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Integrated Device Technology Inc 功能描述: |
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