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参数资料
| 型号： | 74ALVCH6501 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | 18-bit universal bus transceiver(18位通用总线收发器（三态）) |
| 中文描述： | 18位通用总线收发器（18位通用总线收发器（三态）） |
| 文件页数： | 2/13页 |
| 文件大小： | 86K |
| 代理商： | 74ALVCH6501 |
Philips Semiconductors
Product specification
74ALVCH16501
18-bit universal bus transceiver (3-State)
2
1998 Sep 29
853–2091 20106
FEATURES
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
±
24 mA at 3.0 V
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched or clocked mode.
All inputs have bushold circuitry
Output drive capability 50
transmission lines @ 85
°
C
3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16501 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OE
AB
and OE
BA
), latch enable (LE
AB
and LE
BA
), and clock
(CP
AB
and CP
BA
) inputs. For A-to-B data flow, the device operates
in the transparent mode when LE
AB
is High. When LE
AB
is Low, the
A data is latched if CP
AB
is held at a High or Low logic level. If LE
AB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CP
AB
. When OE
AB
is High, the outputs are
active. When OE
AB
is Low, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B but uses OE
BA
, LE
BA
and CP
BA
. The output enables are complimentary (OE
AB
is active
High, and OE
BA
is active Low).
To ensure the high impedance state during power up or power
down, OE
BA
should be tied to V
CC
through a pullup resistor and
OE
AB
should be tied to GND through a pulldown resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
= 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An, Bn to Bn, An
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.8
3.0
ns
C
I/O
C
I
Input/output capacitance
8.0
pF
Input capacitance
4.0
pF
C
PD
Power dissipation capacitance per
latch
V
I
= GND to V
CC1
Outputs enabled
21
pF
Outputs disabled
3
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V; (C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
74ALVCH16501 DGG
DWG NUMBER
SOT364-1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 74ALVCHG162280GRE4 | 功能描述:通用总线函数 16-32B Reg Bus Exchanger RoHS:否 制造商:Texas Instruments 逻辑类型:CMOS 逻辑系列:74VMEH 电路数量:1 开启电阻（最大值）: 传播延迟时间:10.1 ns 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大工作温度:+ 85 C 最小工作温度:0 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74ALVCHG162280GRG4 | 功能描述:通用总线函数 16-32B Reg Bus Exchanger RoHS:否 制造商:Texas Instruments 逻辑类型:CMOS 逻辑系列:74VMEH 电路数量:1 开启电阻（最大值）: 传播延迟时间:10.1 ns 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大工作温度:+ 85 C 最小工作温度:0 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74ALVCHG162282GRE4 | 功能描述:通用总线函数 18-36B Reg Bus Exchanger RoHS:否 制造商:Texas Instruments 逻辑类型:CMOS 逻辑系列:74VMEH 电路数量:1 开启电阻（最大值）: 传播延迟时间:10.1 ns 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大工作温度:+ 85 C 最小工作温度:0 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74ALVCHG162282GRG4 | 功能描述:通用总线函数 18-36B Reg Bus Exchanger RoHS:否 制造商:Texas Instruments 逻辑类型:CMOS 逻辑系列:74VMEH 电路数量:1 开启电阻（最大值）: 传播延迟时间:10.1 ns 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大工作温度:+ 85 C 最小工作温度:0 C 封装 / 箱体:TSSOP-48 封装:Reel |
| 74ALVCHR162245A4PA | 制造商:Rochester Electronics LLC 功能描述: 制造商:Integrated Device Technology Inc 功能描述: |
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