参数资料
型号: 74ALVT16260
厂商: NXP Semiconductors N.V.
英文描述: 12-bit to 24-bit multiplexed D-type latches(3-State)(12位至 24位多路D锁存器(三态))
中文描述: 12位至24位复用D型锁存器(3态)(12位至24位多路?锁存器(三态))
文件页数: 2/14页
文件大小: 91K
代理商: 74ALVT16260
Philips Semiconductors
Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
2
1998 Jan 30
853-2046-18918
FEATURES
ESD protection exceeds 2000V per Mil-Std-883C, Method 3015;
exceeds 200V using machine model
Latch-up protection exceeds 500mA per JEDEC Standard
JESD-17.
Distributed V
CC
and GND pin configuration minimizes high-speed
switching noise.
Output capability (–32mA I
OH
, 64mA I
OL
).
Bus hold inputs eliminate the need for external pull-up resistors.
5V I/O compatible
Live insertion/extraction permitted
Power-up 3-State
Power-up Reset
DESCRIPTION
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used
in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications
include multiplexing and/or demultiplexing of address and data
information in microprocessor or bus-interface applications. This
device is alto useful in memory-interleaving applications.
Three 12-bit I/O ports (A1–A12, 1B1–1B12, and 2B1–2B12) are
available for address and/or data transfer. The output enable (OE1B,
OE2B, and OEA) inputs control the bus transceiver functions. The
OE1B and OE2B control signals also allow bank control in the A to
B direction.
Address and/or data information can be stored using the internal
storage latches. The latch enable (LE1B, LE2B, LEA1B, and
LEA2B) inputs are used to control data storage. When the latch
enable input is high, the latch is transparent. When the latch enable
input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.
To ensure the high-impedance state during power-up or
power-down, OE should be tied to V
CC
through a pull-up resistor;
the minimum value of the resistor is determined by the current
sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline
Package (SSOP) and 56-pin Thin Shrink Small Outline Package
(TSSOP).
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
2.5V
3.3V
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
Propagation delay
C = 50 pF
3.5
2.8
ns
nAx to nBx nBx to nAx
3.3
2.6
Input capacitance
V
I
= 0 V or V
CC
V
I/O
= 0 V or 5.0 V
Outputs disabled
4
4
pF
Output capacitance
9
9
pF
Total supply current
100
80
μ
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
–40
°
C to +85
°
C
74ALVT16260 DL
AV16260 DL
SOT371-1
56-Pin Plastic TSSOP Type II
74ALVT16260 DGG
AV16260 DGG
SOT364-1
相关PDF资料
PDF描述
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相关代理商/技术参数
参数描述
74ALVT16260DG 功能描述:闭锁 12-BIT TO 24-BIT MULITPLEXED D RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel
74ALVT16260DGG 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:12-bit to 24-bit multiplexed D-type latches 3-State
74ALVT16260DGG,112 功能描述:闭锁 12-BIT TO 24-BIT RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel
74ALVT16260DGG,118 功能描述:闭锁 12-BIT TO 24-BIT RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel
74ALVT16260DG-T 功能描述:闭锁 12-BIT TO 24-BIT MULITPLEXED D RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel