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参数资料
| 型号： | 74ALVT16600 |
| 厂商： | NXP Semiconductors N.V. |
| 英文描述： | 2.5V/3.3V 18-bit universal bus transceiver 3-State |
| 中文描述： | 2.5V/3.3V的18位通用总线收发器，三态 |
| 文件页数： | 2/14页 |
| 文件大小： | 97K |
| 代理商： | 74ALVT16600 |
Philips Semiconductors
Product specification
74ALVT16600
2.5V/3.3V 18-bit universal bus transceiver (3-State)
2
1998 Feb 13
853-1979 18958
FEATURES
18-bit bidirectional bus interface
5V I/O Compatible
3-State buffers
Output capability: +64mA/-32mA
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5V bus
Negative edge-triggered clock inputs
Latch-up protection exceeds 500mA per JEDEC JC40.2 Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ALVT16600 is a high-performance BiCMOS product
designed for V
CC
operation at 2.5V and 3.3V with I/O compatibility
up to 5V.
This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and
OEBA), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
High-to-Low transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The High clock can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA,
LEBA and CPBA.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C
TYPICAL
UNIT
2.5V
3.3V
t
PLH
t
PHL
Propagation delay
An to Bn or Bn to An
C
L
= 50pF
1.9
2.5
1.6
1.9
ns
C
IN
Input capacitance DIR, OE
V
I
= 0V or V
CC
4
4
pF
C
I/O
I/O pin capacitance
Outputs disabled; V
I/O
= 0V or V
CC
8
8
pF
I
CCZ
Total supply current
Outputs disabled
40
70
μ
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ALVT16600 DL
AV16600 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ALVT16600 DGG
AV16600 DGG
SOT364-1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1, 27
OEAB/OEBA
A-to-B Output enable input (active Low)
29, 56
CEBA/CEAB
B-to-A / A-to-B clock enable (active Low)
2, 28
LEAB/LEBA
A-to-B/B-to-A Latch enable input
55,30
CPAB/CPBA
A-to-B/B-to-A Clock input (active falling edge)
3, 5, 6, 8, 9, 10, 12, 13, 14, 15,
16, 17, 19, 20, 21, 23, 24, 26
A0-A17
Data inputs/outputs (A side)
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
B0-B17
Data inputs/outputs (B side)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
相关PDF资料 |
PDF描述 |
|---|---|
| 74ALVT16600DGG | 2.5V/3.3V 18-bit universal bus transceiver 3-State |
| 74ALVT16600DL | Hex Schmitt-Trigger Inverters 14-SOIC -40 to 85 |
| 74ALVT16601 | Hex Schmitt-Trigger Inverters 14-SSOP -40 to 85 |
| 74ALVT16646 | Hex Schmitt-Trigger Inverters 14-SOIC -40 to 85 |
| 74ALVT166646DL | 2.5V/3.3V 16-bus transceiver 3-State |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 74ALVT16600DGG | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5V/3.3V 18-bit universal bus transceiver 3-State |
| 74ALVT16600DL | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5V/3.3V 18-bit universal bus transceiver 3-State |
| 74ALVT16600DL-T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:18-Bit Bus Transceiver |
| 74ALVT16601 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:18-bit universal bus transceiver; 3-state |
| 74ALVT16601_05 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:18-bit universal bus transceiver; 3-state |
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