参数资料
型号: 74ALVT16823
厂商: NXP Semiconductors N.V.
英文描述: 18-bit bus-interface D-type flip-flop with reset and enable (3-State)(带复位和使能的18位总线接口D触发器(三态))
中文描述: 18位总线接口D型触发器的复位触发器,使(3态)(带复位和使能的18位总线接口?触发器(三态))
文件页数: 2/12页
文件大小: 99K
代理商: 74ALVT16823
Philips Semiconductors
Product specification
74ALVT16823
2.5V/3.3V 18-bit bus-interface D-type flip-flop
with reset and enable (3-State)
2
1998 Jun 12
853-2069 19558
FEATURES
Two sets of high speed parallel registers with positive
edge-triggered D-type flip-flops
5V I/O Compatible
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Live insertion/extraction permitted
Power-up 3-State
Power-up Reset
No bus current loading when output is tied to 5 V bus
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ALVT16823 18-bit bus interface register is designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider data/address paths of buses
carrying parity.
The 74ALVT16823 has two 9-bit wide buffered registers with Clock
Enable (nCE) and Master Reset (nMR) which are ideal for parity bus
interfacing in high microprogrammed systems.
The registers are fully edge-triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
It is designed for V
CC
operation from 2.5 V to 3.0 V with I/O
compatibility to 5 V.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C; GND = 0V
TYPICAL
UNIT
2.5V
3.3V
t
PLH
t
PHL
Propagation delay
nCP to nQx
C
L
= 50pF
2.5
1.9
ns
C
IN
Input capacitance
V
I
= 0V or V
CC
3
3
pF
C
OUT
Output capacitance
V
I/O
= 0V or 3.0V
9
9
pF
I
CCZ
Total supply current
Outputs disabled
40
70
μ
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ALVT16823 DL
AV16823 DL
SOT371–1
56-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ALVT16823 DGG
AV16823 DGG
SOT364–1
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2, 27
1OE, 2OE
Output enable input (active-Low)
54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31
1D0-1D8
2D0-2D8
Data inputs
3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26
1Q0-1Q8
2Q0-2Q8
Data outputs
56, 29
1CP, 2CP
Clock pulse input (active rising edge)
55, 30
1CE, 2CE
Clock enable input (active-Low)
1, 28
1MR, 2MR
Master reset input (active-Low)
4, 11, 18, 25, 32, 39, 46, 53
GND
Ground (0V)
7, 22, 35, 50
V
CC
Positive supply voltage
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