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参数资料
| 型号： | 74ALVT16841DGG |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 通用总线功能 |
| 英文描述： | Hex Schmitt-Trigger Inverters 14-TSSOP -40 to 85 |
| 中文描述： | ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 文件页数： | 2/14页 |
| 文件大小： | 96K |
| 代理商： | 74ALVT16841DGG |
Philips Semiconductors
Product specification
74ALVT16841
2.5V/3.3V 20-bit bus interface latch (3-State)
2
1998 Feb 13
853-1868 18961
FEATURES
High speed parallel latches
5V I/O Compatible
Live insertion/extraction permitted
Extra data width for wide address/data paths or buses carrying
parity
Power-up 3-State
Power-up reset
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per Jedec Std 17
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ALVT16841 Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity. It is
designed for V
CC
operation at 2.5V or 3.3V with I/O compatibility to
5V.
The 74ALVT16841 consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
T
amb
= 25
°
C
TYPICAL
UNIT
2.5V
3.3V
t
PLH
t
PHL
Propagation delay
nDx to nQx
C
L
= 50pF
1.8
2.1
1.5
1.7
ns
C
IN
Input capacitance DIR, OE
V
I
= 0V or V
CC
3
3
pF
C
Out
Output pin capacitance
V
I/O
= 0V or V
CC
9
9
pF
I
CCZ
Total supply current
Outputs disabled
40
70
μ
A
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°
C to +85
°
C
74ALVT16841 DL
AV16841 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°
C to +85
°
C
74ALVT16841 DGG
AV16841 DGG
SOT364-1
相关PDF资料 |
PDF描述 |
|---|---|
| 74ALVT16841 | 2.5V/3.3V ALVT 20-bit bus interface latch(3-State)(2.5V/3.3V ALVT 20位总线接口锁存器（三态）) |
| 74ALVT16841DL | 2.5V/3.3V ALVT 20-bit bus interface latch 3-State |
| 74ALVT16899 | 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker (3-State)(带16位奇偶发生器/校验器的2.5V/3.3V 18位锁存收发器（三态）) |
| 74ALVT16899DGG | 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 74ALVT16952 | 2.5V/3.3V 16-bit registered transceiver (3-State)(2.5V/3.3V16位寄存收发器（三态）) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 74ALVT16841DL | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5V/3.3V ALVT 20-bit bus interface latch 3-State |
| 74ALVT16841DL-T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:10-Bit D-Type Latch |
| 74ALVT16899 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker 3-State |
| 74ALVT16899DGG | 制造商:NXP Semiconductors 功能描述: |
| 74ALVT16899DGG-T | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Dual 8-bit Bus Transceiver |
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