参数资料
型号: 74AUC1G02
英文描述: 74AUC1G02 Single 2-input NOR gate
中文描述: 74AUC1G02单2输入或非门
文件页数: 2/12页
文件大小: 50K
代理商: 74AUC1G02
2002 Nov 12
2
Philips Semiconductors
Preliminary specification
Single 2-input NAND gate
74AUC1G00
FEATURES
Wide supply voltage range from 0.8 to 2.7 V
Performance optimised for V
CC
= 1.8 V
High noise immunity
Complies with JEDEC standard:
– JESD76 (1.65 to 1.95 V)
8 mA output drive (V
CC
= 1.65 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
ESD protection:
2000 V Human Body Model (A 114-A)
200 V Machine Model (A 115-A)
3.3 V tolerant inputs/outputs
SC-88A and SC-74A package.
DESCRIPTION
The 74AUC1G00 is a high-performance, low-power,
low-voltage, Si-gate CMOS device.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging current backflow through the
device when it is powered down.
The 74AUC1G00 provides the single 2-input NAND
function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; input slewrate
1 V/ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+ (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay inputs A and B to
output Y
V
CC
= 0.8 V; C
L
= 15 pF; R
L
= 2 k
V
CC
= 1.2 V; C
L
= 15 pF; R
L
= 2 k
V
CC
= 1.5 V; C
L
= 15 pF; R
L
= 2 k
V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 k
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
4.7
1.8
1.4
1.4
1.2
4
14
ns
ns
ns
ns
ns
pF
pF
C
I
C
PD
input capacitance
power dissipation capacitance per buffer
V
CC
= 1.8 V; notes 1 and 2
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