参数资料
| 型号： | 74HC112DB,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 8/15页 |
| 文件大小： | 0K |
| 描述： | IC DUAL JK F-F NEG-EDGE 16SSOP |
| 产品培训模块： | Logic Packages |
| 标准包装： | 2,000 |
| 系列： | 74HC |
| 功能： | 设置（预设）和复位 |
| 类型： | JK 型 |
| 输出类型： | 差分 |
| 元件数： | 2 |
| 每个元件的位元数： | 1 |
| 频率 - 时钟： | 71MHz |
| 延迟时间 - 传输： | 16ns |
| 触发器类型： | 负边沿 |
| 输出电流高，低： | 5.2mA，5.2mA |
| 电源电压： | 2 V ~ 6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.209"，5.30mm 宽） |
| 包装： | 带卷 (TR) |
| 其它名称： | 74HC112DB-T 74HC112DB-T-ND 935189200118 |
1998 Jun 10
2
Philips Semiconductors
Product specication
Dual JK ip-op with set and reset;
negative-edge trigger
74HC/HCT112
FEATURES
Asynchronous set and reset
Output capability: standard
ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nSD) and reset (nRD) inputs.
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5 V
nCP to nQ, nQ
1719ns
nSD to nQ, nQ
1515ns
nRD to nQ, nQ
1819ns
fmax
maximum clock frequency
66
70
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per ip-op
notes 1 and 2
27
30
pF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 74HC112DB-T | 功能描述:触发器 DUAL J-K NEG EDGE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| 74HC112D-T | 功能描述:触发器 DUAL J-K NEG EDGE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| 74HC112E | 制造商:Texas Instruments 功能描述: |
| 74HC112N | 功能描述:触发器 DUAL J-K NEG EDGE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
| 74HC112N,652 | 功能描述:触发器 DUAL J-K NEG EDGE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
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