参数资料
型号: 74HC4017PW,118
厂商: NXP Semiconductors
文件页数: 1/24页
文件大小: 0K
描述: IC JOHNSON DECADE COUNT 16TSSOP
产品培训模块: Logic Packages
标准包装: 2,500
系列: 74HC
逻辑类型: 计数器,十进制
方向:
元件数: 1
每个元件的位元数: 10
复位: 异步
计数速率: 83MHz
触发器类型: 正边沿
电源电压: 2 V ~ 6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
其它名称: 74HC4017PW-T
74HC4017PW-T-ND
935189080118
1.
General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded
outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs
(CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is
advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a
HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9
output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive
the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 =
HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code
correction of the counter is provided by an internal circuit: following any illegal code the
counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2.
Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
For 74HC4017: CMOS level
For 74HCT4017: TTL level
Complies with JEDEC standard no. 7 A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 Cto+85 C and from 40 Cto+125 C
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 4 — 10 December 2013
Product data sheet
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