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参数资料
| 型号： | 74HC4353U |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 多路复用及模拟开关 |
| 英文描述： | TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, UUC |
| 文件页数： | 9/16页 |
| 文件大小： | 124K |
| 代理商： | 74HC4353U |
December 1990
2
Philips Semiconductors
Product specication
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
FEATURES
Wide analog input voltage range: ± 5 V
Low “ON” resistance:
80
(typ.) at VCC VEE = 4.5 V
70
(typ.) at VCC VEE = 6.0 V
60
(typ.) at VCC VEE = 9.0 V
Logic level translation:
to enable 5 V logic to communicate with
± 5 V analog
signals
Typical “break before make” built in
Address latches provided
Output capability: non-standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4353 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4353 are triple 2-channel analog
multiplexers/demultiplexers with two common enable
inputs (E1 and E2) and a latch enable input (LE). Each
multiplexer has two independent inputs/outputs (nY0 and
nY1), a common input/output (nZ) and select inputs (S1 to
S3).
Each multiplexer/demultiplexer contains two bidirectional
analog switches, each with one side connected to an
independent input/output (nY0 and nY1) and the other side
connected to a common input/output (nZ).
With E1 LOW and E2 HIGH, one of the two switches is
selected (low impedance ON-state) by S1 to S3.
The data at the select inputs may be latched by using the
active LOW latch enable input (LE). When LE is HIGH, the
latch is transparent. When either of the two enable inputs,
E1 (active LOW) and E2 (active HIGH), is inactive, all
analog switches are turned off.
VCC and GND are the supply voltage pins for the digital
control inputs (S1 to S3, LE, E1 and E2). The VCC to GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY0 and nY1, and nZ) can
swing between VCC as a positive limit and VEE as a
negative limit. VCC VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is
connected to GND (typically ground).
QUICK REFERENCE DATA
VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPZH/ tPZL
turn “ON” time E1,E2 or Sn to Vos
CL = 50 pF; RL =1 k;
VCC = 5 V
29
21
ns
tPHZ/ tPLZ
turn “OFF” time E1,E2 or Sn to Vos
20
22
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per switch
notes 1 and 2
23
pF
CS
max. switch capacitance
independent (Y)
5
pF
common (Z)
8
pF
Notes
1. CPD is used to determine the dynamic power
dissipation (PD in W):
PD =
CPD × VCC2 × fi + ∑ {(CL +CS) × VCC2 × fo} where:
fi = input frequency in MHz
CL = output load capacitance in pF
fo = output frequency in MHz
CS = max. switch capacitance in pF
∑ {(CL ×CS) × VCC2 × fo} = sum of outputs
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package
Information”.
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