参数资料
型号: 74HC58DB,118
厂商: NXP Semiconductors
文件页数: 2/5页
文件大小: 0K
描述: IC GATE AND-OR DUAL 14SSOP
产品培训模块: Logic Packages
标准包装: 1
系列: 74HC
逻辑类型: 与/或门
电路数: 2
输入数: 10 输入(3,3,2,2)
施密特触发器输入:
输出类型: 单端
安装类型: 表面贴装
封装/外壳: 14-SSOP(0.209",5.30mm 宽)
供应商设备封装: 14-SSOP
包装: 标准包装
其它名称: 568-8894-6
December 1990
2
Philips Semiconductors
Product specication
Dual AND-OR gate
74HC58
FEATURES
Output capability: standard
ICC category: SSI
GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 15 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
∑ (CL × VCC2 × fo) = sum of outputs
2. For HC the condition is VI = GND to VCC
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC = 5 V
1n to 1Y
11
ns
2n to 2Y
9
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per
gate
notes 1 and 2
18
pF
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相关代理商/技术参数
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74HC58N 制造商:NXP Semiconductors 功能描述:DUAL AND/OR GATE
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