参数资料
| 型号： | 74HC93DB,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 2/7页 |
| 文件大小： | 0K |
| 描述： | IC 4B BINARY RIPPL COUNT 14SSOP |
| 产品培训模块： | Logic Packages |
| 标准包装： | 78 |
| 系列： | 74HC |
| 逻辑类型： | 二进制计数器 |
| 方向： | 上 |
| 元件数： | 1 |
| 每个元件的位元数： | 4 |
| 复位： | 异步 |
| 计数速率： | 108MHz |
| 触发器类型： | 负边沿 |
| 电源电压： | 2 V ~ 6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 14-SSOP |
| 包装： | 管件 |
| 其它名称： | 568-2755-5 935190320112 |
December 1990
2
Philips Semiconductors
Product specication
4-bit binary ripple counter
74HC/HCT93
FEATURES
Various counting modes
Asynchronous master reset
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT93 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.
The 74HC/HCT93 are 4-bit binary
ripple counters. The devices consist
of four master-slave flip-flops
internally connected to provide a
divide-by-two section and a
divide-by-eight section. Each section
has a separate clock input (CP0 and
CP1) to initiate state changes of the
counter on the HIGH-to-LOW clock
transition. State changes of the Qn
outputs do not occur simultaneously
because of internal ripple delays.
Therefore, decoded output signals
are subject to decoding spikes and
should not be used for clocks or
strobes.
A gated AND asynchronous master
reset (MR1 and MR2) is provided
which overrides both clocks and
resets (clears) all flip-flops.
Since the output from the
divide-by-two section is not internally
connected to the succeeding stages,
the device may be operated in various
counting modes. In a 4-bit ripple
counter the output Q0 must be
connected externally to input CP1.
The input count pulses are applied to
clock input CP0. Simultaneous
frequency divisions of 2, 4, 8 and 16
are performed at the Q0, Q1, Q2 and
Q3 outputs as shown in the function
table. As a 3-bit ripple counter the
input count pulses are applied to input
CP1.
Simultaneous frequency divisions of
2, 4 and 8 are available at the Q1, Q2
and Q3 outputs. Independent use of
the first flip-flop is available if the reset
function coincides with reset of the
3-bit ripple-through counter.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF; VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP0 to Q0
CL = 15 pF; VCC =5 V
12
15
ns
fmax
maximum clock frequency
100
77
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
22
pF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 74HC93DB-T | 功能描述:计数器 IC 4-BIT BINARY RIPPLE COUNTER RoHS:否 制造商:NXP Semiconductors 计数器类型:Binary Counters 逻辑系列:74LV 位数:10 计数法: 计数顺序: 工作电源电压:1 V to 5.5 V 工作温度范围:- 40 C to + 125 C 封装 / 箱体:SOT-109 封装:Reel |
| 74HC93N | 制造商:NXP Semiconductors 功能描述:HC Counter/Divider 制造商:NXP Semiconductors 功能描述:IC 74HC CMOS 74HC93 DIP14 5V 制造商:NXP Semiconductors 功能描述:IC, 74HC CMOS, 74HC93, DIP14, 5V 制造商:NXP Semiconductors 功能描述:IC, 4BIT BINARY RIPPLE COUNTER, DIP-14; Counter Type:Binary Ripple; Clock Frequency:108MHz; Count Maximum:16; Supply Voltage Min:2V; Supply Voltage Max:6V; Logic Case Style:DIP; No. of Pins:14; Operating Temperature Min:-40C ;RoHS Compliant: Yes |
| 74HC93N,112 | 功能描述:计数器 IC 4-BIT BIN RIP COUNTR RoHS:否 制造商:NXP Semiconductors 计数器类型:Binary Counters 逻辑系列:74LV 位数:10 计数法: 计数顺序: 工作电源电压:1 V to 5.5 V 工作温度范围:- 40 C to + 125 C 封装 / 箱体:SOT-109 封装:Reel |
| 74HC93N | 制造商:NXP Semiconductors 功能描述:IC 74HC CMOS LOGIC |
| 74HC93N112 | 制造商:NXP Semiconductors 功能描述:IC 4BIT BINARY RIPPLE COUNTER DIP-14 |
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