参数资料
型号: 74HCT173D,653
厂商: NXP Semiconductors
文件页数: 2/7页
文件大小: 0K
描述: IC D F-F POS-EDGE TRIGGER 16SOIC
产品培训模块: Logic Packages
标准包装: 2,500
系列: 74HCT
功能: 主复位
类型: D 型总线
输出类型: 三态非反相
元件数: 4
每个元件的位元数: 1
频率 - 时钟: 80MHz
延迟时间 - 传输: 20ns
触发器类型: 正边沿
输出电流高,低: 6mA,6mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
其它名称: 568-8907-2
74HCT173D,653-ND
74HCT173D-T
74HCT173D-T-ND
933715040653
December 1990
2
Philips Semiconductors
Product specication
Quad D-type ip-op; positive-edge trigger; 3-state
74HC/HCT173
FEATURES
Gated input enable for hold (do nothing) mode
Gated output enable control
Edge-triggered D-type register
Asynchronous master reset
Output capability: bus driver
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q0 to Q3)
and master reset (MR).
When the two data enable inputs (E1 and E2) are LOW, the
data on the Dn inputs is loaded into the register
synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both En inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.
The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE1 and OE2) are
LOW, the data in the register is presented to the Qn
outputs. When one or both OEn inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OEn transition does not affect the
clock and reset operations.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf =6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CP to Qn
MR to Qn
CL = 15 pF; VCC =5V
17
13
17
ns
fmax
maximum clock frequency
88
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation
capacitance per ip-op
notes 1 and 2
20
pF
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74HCT173DB 功能描述:触发器 QUAD D-TYPE 3-STATE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
74HCT173DB,112 功能描述:触发器 QUAD D-TYPE 3-STATE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
74HCT173DB,118 功能描述:触发器 QUAD D-TYPE 3-STATE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
74HCT173DB-T 功能描述:触发器 QUAD D-TYPE 3-STATE RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel
74HCT173N 制造商:NXP Semiconductors 功能描述:QUAD D-TYPE F/F 3-STATE