参数资料
型号: 74HCT374PW,112
厂商: NXP Semiconductors
文件页数: 8/8页
文件大小: 0K
描述: IC D-TYPE FF POS-EDG-TRG 20TSSOP
产品培训模块: Logic Packages
标准包装: 1,875
系列: 74HCT
功能: 标准
类型: D 型总线
输出类型: 三态非反相
元件数: 1
每个元件的位元数: 8
频率 - 时钟: 44MHz
延迟时间 - 传输: 16ns
触发器类型: 正边沿
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 管件
74LVCH32245A
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 15 December 2011
8 of 15
NXP Semiconductors
74LVCH32245A
32-bit bus transceiver with direction pin; 5 V tolerant; 3-state
[1]
Typical values are measured at Tamb =25 C and VCC = 1.2, 1.8, 2.5 V, 2.7 V, and 3.3 V respectively.
[2]
tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3]
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD VCC2 fi N+ (CL VCC2 fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(C
L VCC
2
f
o) = sum of the outputs.
11. Waveforms
tdis
disable time
nOE to nAn, nBn; see Figure 5
VCC = 1.2 V
-
11.0
-
ns
VCC = 1.65 V to 1.95 V
1.5
4.9
13.1
1.5
14.7
ns
VCC = 2.3 V to 2.7 V
0.5
2.7
7.1
0.5
7.9
ns
VCC = 2.7 V
1.5
3.4
6.6
1.5
8.5
ns
VCC = 3.0 V to 3.6 V
1.5
3.3
5.6
1.5
7.0
ns
tsk(o)
output skew
time
VCC = 3.0 V to 3.6 V
-
1.0
-
1.5
ns
CPD
power
dissipation
capacitance
per buffer; VI =GND to VCC
VCC = 1.65 V to 1.95 V
-
11.5
-
pF
VCC = 2.3 V to 2.7 V
-
15.2
-
pF
VCC = 3.0 V to 3.6 V
-
18.5
-
pF
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 6.
Symbol Parameter
Conditions
Tamb = 40 C to +85 C 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
VM = 1.5 V at VCC 2.7 V.
VM =0.5 VCC at VCC <2.7 V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4.
The input (nAn, nBn) to output (nBn, nAn) propagation delays
mna477
nAn, nBn
input
nBn, nAn
output
tPHL
tPLH
GND
VI
VM
VOH
VOL
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