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参数资料
型号： 74HCT4510DB
厂商： NXP SEMICONDUCTORS
元件分类： 计数器
英文描述： BCD up/down counter
中文描述： HCT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDSO16
文件页数： 5/12页
文件大小： 102K
代理商： 74HCT4510DB
December 1990
2
Philips Semiconductors
Product specication
BCD up/down counter
74HC/HCT4510
FEATURES
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4510 are high-speed Si-gate CMOS
devices and are pin compatible with the “4510” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4510 are edge-triggered synchronous
up/down BCD counters with a clock input (CP), an
up/down count control input (UP/DN), an active LOW
count enable input (CE), an asynchronous active HIGH
parallel load input (PL), four parallel inputs (D0 to D3), four
parallel outputs (Q0 to Q3), an active LOW terminal count
output (TC), and an overriding asynchronous master reset
input (MR).
Information on D0 to D3 is loaded into the counter while PL
is HIGH, independent of all other input conditions except
the MR input, which must be LOW. With PL LOW, the
counter changes on the LOW-to-HIGH transition of CP if
CE is LOW. UP/DN determines the direction of the count,
HIGH for counting up, LOW for counting down. When
counting up, TC is LOW when Q0 and Q3 are HIGH and CE
is LOW. When counting down, TC is LOW when Q0 to Q3
and CE are LOW. A HIGH on MR resets the counter (Q0 to
Q3 = LOW) independent of all other input conditions.
Logic equation for terminal count:
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay CP to Qn
CL = 15 pF; VCC = 5 V 2123ns
fmax
maximum clock frequency
57
58
MHz
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per package
notes 1 and 2
50
53
pF
TC = CE . {(UP/DN) . Q
0 .Q3 +(UP/DN) . Q0 .Q1 .Q2 .Q3 }
相关PDF资料
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