参数资料
型号: 74HCT9115N,112
厂商: NXP Semiconductors
文件页数: 2/7页
文件大小: 0K
描述: IC BUFF NINE SCHMT TIG 20PDIP
产品培训模块: Logic Packages
标准包装: 18
系列: 74HCT
逻辑类型: 施密特触发器 - 带开漏极的缓冲器
元件数: 9
每个元件的位元数: 1
输出电流高,低: 6mA,6mA
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 通孔
封装/外壳: 20-DIP(0.300",7.62mm)
供应商设备封装: 20-DIP
包装: 管件
其它名称: 568-2918-5
933987860112
December 1990
2
Philips Semiconductors
Product specication
Nine wide Schmitt trigger buffer;
open drain outputs
74HC/HCT9115
FEATURES
Schmitt trigger action on all data inputs
Output capability: standard (open drain)
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT9115 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT9115 are nine wide Schmitt trigger buffer
with open drain outputs and Schmitt trigger inputs.
The Schmitt trigger action in the data inputs transform
slowly changing input signals into sharply defined
jitter-free output signals.
The 74HC/HCT9115 have open-drain N-transistor
outputs, which are not clamped by a diode connected to
VCC. In the OFF-state, i.e. when one input is HIGH, the
output may be pulled to any voltage between GND and
VOmax. This allows the device to be used as a
LOW-to-HIGH or HIGH-to-LOW level shifter. For digital
operation and OR-tied output applications, these devices
must have a pull-up resistor to establish a logic HIGH level.
The “9115” is identical to the “9114” but has non-inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLZ
propagation delay An to Yn
CL = 15 pF; VCC = 5 V
12
13
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per buffer
notes 1 and 2
5
pF
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