参数资料
型号: 74LCX11SJX
厂商: Fairchild Semiconductor
文件页数: 1/13页
文件大小: 0K
描述: IC GATE AND TRPL 3IN LV 14SOP
标准包装: 2,000
系列: 74LCX
逻辑类型: 与门
电路数: 3
输入数: 3
电源电压: 2 V ~ 3.6 V
电流 - 静态(最大值): 10µA
输出电流高,低: 24mA,24mA
逻辑电平 - 低: 0.7 V ~ 0.8 V
逻辑电平 - 高: 1.7 V ~ 2 V
额定电压和最大 CL 时的最大传播延迟: 6ns @ 3.3V,50pF
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
供应商设备封装: 14-SOIC
封装/外壳: 14-SOIC(0.209",5.30mm 宽)
包装: 带卷 (TR)
74LCX11
Lo
w
V
olta
g
e
T
riple
3-Input
AND
Gate
with
5V
T
olerant
Inputs
1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX11 Rev. 1.6.1
74LCX11
Low Voltage Triple 3-Input AND Gate with 5V
Tolerant Inputs
Features
5V tolerant inputs
2.3V–3.6V VCC specifications provided
6.0ns tPD max. (VCC = 3.3V), 10A ICC max.
Power down high impedance inputs and outputs
±24mA output drive (VCC = 3.0V)
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model
> 2000V
– Machine model
> 200V
Leadless DQFN package
General Description
The LCX11 is a triple 3-input AND gate with buffered
outputs. LCX devices are designed for low voltage (2.5V
or 3.3V) operation with the added capability of interfac-
ing to a 5V signal environment.
The 74LCX11 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Ordering Information
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number
Package Description
74LCX11M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX11SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX11BQX(1)
MLP14A
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
74LCX11MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Implements proprietary noise/EMI reduction circuitry
December 2013
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