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| 型号： | 74LCX16240MTDX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 5/8页 |
| 文件大小： | 0K |
| 描述： | IC INVERTER DUAL 8-INPUT 48TSSOP |
| 标准包装： | 1,000 |
| 系列： | 74LCX |
| 逻辑类型： | 逆变器，缓冲器 |
| 电路数： | 4 |
| 输入数： | 4 |
| 特点： | 三态 |
| 电源电压： | 2 V ~ 3.6 V |
| 电流 - 静态（最大值）： | 20µA |
| 输出电流高，低： | 24mA，24mA |
| 逻辑电平 - 低： | 0.7 V ~ 0.8 V |
| 逻辑电平 - 高： | 1.7 V ~ 2 V |
| 额定电压和最大 CL 时的最大传播延迟： | 4.5ns @ 3.3V，50pF |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 供应商设备封装： | 48-TSSOP |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 包装： | 带卷 (TR) |
5
Commercial Temperature Range
IDT72V8985 3.3V Time Slot Interchange
Digital Switch 256 x 256
making use of a multiple Data Memory buffer technique where input channels
written in any of the buffers during frame N will be read out during frame N+2.
In the IDT72V8985, the minimum throughput delay achievable in Constant
Delay mode will be 32 time slots; for example, when input time slot 32 (channel
31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay
is achieved when the first time slot in a frame (channel 0) is switched to the last
time slot in the frame (channel 31), resulting in 94 time slots of delay (see
Figure 4).
Tosummarize,anyinputtimeslotfrominputframeNwillbealwaysswitched
to the destination time slot on output frame N+2. In Constant Delay mode the
device throughput delay is calculated according to the following formula:
DELAY=[32+(32-IN)+(OUT-1)]
IN =the number of the input time slot (from 1 to 32)
OUT = the number of the output time slot (from 1 to 32).
MICROPROCESSOR PORT
The IDT72V8985 microprocessor port is a non-multiplexed bus architec-
ture. Theparallelportconsistsofan8-bitparalleldatabus(D0-D7),sixaddress
input lines (A0-A5) and four control lines (
CS,DS,R/WandDTA). Thisparallel
microportallowstheaccesstotheControlRegisters,ConnectionMemoryLow,
ConnectionMemoryHigh,andtheDataMemory. Alllocationsareread/written
except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
Memory are multiplexed with accesses from the input and output TDM ports.
This can cause variable Data Acknowledge delays (
DTA). IntheIDT72V8985
device, the
DTAoutputprovidesamaximumacknowledgmentdelayof800ns
for read/write operations in the Connection Memory. However, for operations
in the Data Memory (Processor Mode), the maximum acknowledgment delay
can be 1220ns.
SOFTWARE CONTROL
IftheA5,A1,A0addresslineinputsareLOWthentheIDT72V8985Internal
Control Register is addressed (see Table 2). If A5 input line is high, then the
remaining address input lines are used to select the 32 possible channels per
input or output stream. As explained in the Control Register description, the
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8985 Data and
Connect memories. See Figure 5 for accessing internal memories.
The data in the control register consists of Memory Select and Stream
Addressbits,SplitMemoryandProcessorEnablebits(Table3).InSplitMemory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory LOW. The Memory Select bits allow the
Connection Memory High or LOW or the Data Memory to be chosen, and the
StreamAddressbitsdefineinternalmemorysubsectionscorrespondingtoinput
or output streams.
The Processor Enable bit (bit 6) places every output channel on every
output stream in Processor Mode; i.e., the contents of the Connection Memory
LOW (CML, see Table 5) are output on the output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8985
behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every
Connection Memory High (CMH, see Table 4) locations were set to HIGH,
regardlessoftheactualvalue. IfPEisLOW,thenbit2and0ofeachConnection
MemoryHighlocationoperatesnormally. Inthiscase,ifbit2oftheCMHisHIGH,
the associated TX output channel is in Processor Mode. If bit 2 of the CMH is
LOW, then the contents of the CML define the source information (stream and
channel) of the time slot that is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)
or disables (if LOW) for that particular channel.
Thecontentsofbit1(CCO)ofeachConnectionMemoryHighLocation(see
Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/
s output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit
on CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on
theCCOoutputistransmittedLOW. Thecontentsofthe256CCObitsoftheCMH
are transmitted sequentially on to the CCO output pin and are synchronous to
the TX streams. To allow for delay in any external control circuitry the contents
of the CCO bit is output one channel before the corresponding channel on the
TXstreams. Forexample,thecontentsofCCObitinposition0(corresponding
to TX0, CH0), is transmitted synchronously with the TX channel 31, bit 7. Bit 1's
of CMH for channel 1 of streams 0-7 are output synchronously with TX channel
0 bits 7-0.
INITIALIZATION
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
intothehighimpedancestate. CareshouldbetakenthatnotwoConnectedTX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
The reset pin is designed to be used with board reset circuitry. During reset
the TX serial streams will be put into high-impedance and the state of internal
registers and counters will be reset. As the connection memory can be in any
state after a power up, the ODE pin should be used to hold the TX streams in
high-impedance until the per-channel output enable control in the connection
memoryhighisappropriatelyprogrammed.ThemaindifferencebetweenODE
and reset is, reset alters the state of the registers and counters where as ODE
controls only the high-impedance state of the TX streams.
RESETinputisonly
provided on the SSOP packages.
TABLE 1
VARIABLE DELAY MODE
Input Channel
Output Channel
Throughput Delay
n
m=n, n+1 or n+2
m-n+32 time slot
n
m>n+2
m-n time slot
n
m<n
32-(n-m) time slot
TABLE 2
ADDRESS MAPPING
A5
A4
A3
A2
A1
A0
LOCATION
0
X
0
Control Register
1
00000
Channel 0
1
00001
Channel 1
1
1
1
1
1
1
11111
Channel 31
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