参数资料
型号: 74LCX38SJX
厂商: Fairchild Semiconductor
文件页数: 1/7页
文件大小: 0K
描述: IC GATE NAND QUAD 2IN OD 14SOP
标准包装: 2,000
系列: 74LCX
逻辑类型: 与非门
电路数: 4
输入数: 2
特点: 开路漏极
电源电压: 2 V ~ 3.6 V
电流 - 静态(最大值): 10µA
输出电流高,低: -,24mA
逻辑电平 - 低: 0.7 V ~ 0.8 V
逻辑电平 - 高: 1.7 V ~ 2 V
额定电压和最大 CL 时的最大传播延迟: 5ns @ 3.3V,50pF
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
供应商设备封装: 14-SOIC
封装/外壳: 14-SOIC(0.209",5.30mm 宽)
包装: 带卷 (TR)
2005 Fairchild Semiconductor Corporation
DS012574
www.fairchildsemi.com
October 1995
Revised February 2005
7
4LCX38
Low
V
o
ltage
Quad
2-
Input
NAN
D
Gate
(Open
Drai
n)
wit
h
5
V
T
o
le
rant
Input
s
74LCX38
Low Voltage Quad 2-Input NAND Gate (Open Drain)
with 5V Tolerant Inputs
General Description
The LCX38 contains four 2-input open drain NAND gates.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
The 74LCX38 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs
s 2.3V to 3.6V VCC specifications provided
s 5.0 ns tPD max (VCC 3.3V), 10 PA ICC max
s Power down high impedance inputs and outputs
s 24 mA output drive (VCC 3.0V)
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model
! 2000V
Machine model
! 150V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
Package
Package Description
Number
74LCX38M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX38MX_NL
(Note 1)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX38SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX38MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX38MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names
Description
An, Bn
Inputs
On
Outputs
s Implements proprietary noise/EMI reduction circuitry
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