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参数资料
| 型号： | 74LCX573WM |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | IC LATCH OCT LV 5V I/O 20SOIC |
| 标准包装： | 36 |
| 系列： | 74LCX |
| 逻辑类型： | D 型透明锁存器 |
| 电路： | 8:8 |
| 输出类型： | 三态 |
| 电源电压： | 2 V ~ 3.6 V |
| 独立电路： | 1 |
| 延迟时间 - 传输： | 1.5ns |
| 输出电流高，低： | 24mA，24mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LCX573 Rev. 1.6.1
2
74LCX573
—
Lo
w
V
olta
g
e
Octal
Latc
h
with
5V
T
olerant
Inputs
and
Outputs
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Pad Assignments for DQFN
(Top View)
Pin Descriptions
Logic Symbol
Truth Table
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of
Latch Enable
Functional Description
The LCX573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When
LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode but this does not
interfere with entering new data into the latches.
Pin Names
Description
D0–D7
Data Inputs
LE
Latch Enable Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Latch Outputs
D1
D2
D3
D4
D5
D6
D7
GND
D0
O1
O2
O3
O4
O5
O6
O7
O0
LE
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
D1
D2
D3
D4
D5
D6
D7
GND
D0
O1
O2
O3
O4
O5
O6
O7
LE
O0
VCC
120
2
3
4
5
6
7
8
9
10
11
19
18
17
16
15
14
13
12
OE
Inputs
Outputs
OE
LE
D
On
LH
H
LH
L
LL
X
O0
HX
X
Z
D0 D1 D2 D3 D4 D5 D6 D7
O0
OE
LE
O1 O2 O3 O4 O5 O6 O7
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
D0
O0
D
Q
LE
OE
D1
O1
D
Q
LE
D2
O2
D
Q
LE
D3
O3
D
Q
LE
D4
O4
D
Q
LE
D5
O5
D
Q
LE
D6
O6
D
Q
LE
D7
O7
D
Q
LE
(Bottom View)
DAP
No Connect
Note: DAP (Die Attach Pad)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 74LCX573WM | 制造商:Fairchild Semiconductor Corporation 功能描述:74LCX CMOS SMD 74LCX573 SOIC20 |
| 74LCX573WM_08 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Low Voltage Octal Latch with 5V Tolerant Inputs and Outputs |
| 74LCX573WM_Q | 功能描述:闭锁 Octal Latch RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| 74LCX573WMX | 功能描述:闭锁 Octal Latch RoHS:否 制造商:Micrel 电路数量:1 逻辑类型:CMOS 逻辑系列:TTL 极性:Non-Inverting 输出线路数量:9 高电平输出电流: 低电平输出电流: 传播延迟时间: 电源电压-最大:12 V 电源电压-最小:5 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:SOIC-16 封装:Reel |
| 74LCX574 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:OCTAL D-TYPE FLIP FLOP NON-INVERTING (3-STATE) WITH 5V TOLERANT INPUTS AND OUTPUTS |
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