参数资料
型号: 74LCXH162244MEA
厂商: Fairchild Semiconductor
文件页数: 9/9页
文件大小: 0K
描述: IC BUFF DVR 16BIT LOW V 48SSOP
产品变化通告: Die Material/Mold Compound Change 10/Sept/2008
标准包装: 29
系列: 74LCXH
逻辑类型: 缓冲器/线路驱动器,非反相
元件数: 4
每个元件的位元数: 4
输出电流高,低: 12mA,12mA
电源电压: 2 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-BSSOP(0.295",7.50mm 宽)
供应商设备封装: 48-SSOP
包装: 管件
9
COMMERCIALTEMPERATURERANGE
IDT72V70180 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 128 x 128
TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS
0123
4
5
6
7
8
9
10
11
12
13
14
15
16
ST-BUS Frame
CLK
Offset Value
FE Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GCI Frame
CLK
Offset Value
FE Input
(FD[10:0] = 06H)
(FD11 = 0, sample at CLK LOW phase)
(FD[10:0] = 09H)
(FD11 = 1, sample at CLK HIGH phase)
5716 drw04
Figure 4. Example for Frame Alignment Measurement
Bit
Name
Description
15-13
Unused
Must be zero for normal operation.
12
CFE
When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment
(Complete Frame Evaluation)
offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.
11
FD11
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)
(Frame Delay Bit 11)
or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to CLK cycle.
10-0
FD10-0
The binary value expressed in these bits refers to the measured input offset value. These bits are rest to
(Frame Delay Bits)
zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
Read/Write Address:
02H.
Reset Value:
0000H.
15
14
13
12
11
10
9876543210
0
CFE
FD11
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
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