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参数资料
| 型号： | 74LVC163DB,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 1/20页 |
| 文件大小： | 0K |
| 描述： | IC SYNC 4BIT BIN COUNTER 16SSOP |
| 产品培训模块： | Logic Packages |
| 标准包装： | 2,000 |
| 系列： | 74LVC |
| 逻辑类型： | 二进制计数器 |
| 方向： | 上 |
| 元件数： | 1 |
| 每个元件的位元数： | 4 |
| 复位： | 同步 |
| 计时： | 同步 |
| 计数速率： | 150MHz |
| 触发器类型： | 正边沿 |
| 电源电压： | 1.2 V ~ 3.6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 74LVC163DB-T 74LVC163DB-T-ND 935210550118 |
1.
General description
The 74LVC163 is a synchronous presettable binary counter which features an internal
look-ahead carry and can be used for high-speed counting. Synchronous operation is
provided by having all flip-flops clocked simultaneously on the positive-going edge of the
clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level
or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting
action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter
on the positive-going edge of the clock (provided that the set-up and hold time
requirements for PE are met). Preset takes place regardless of the levels at count enable
inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all four
outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going
transition on the clock input (pin CP) (provided that the set-up and hold time requirements
for PE are met). This action occurs regardless of the levels at input pins PE, CET and
CEP. This synchronous reset feature enables the designer to modify the maximum count
with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs
(pin CEP and CET) must be HIGH in count. The CET input is fed forward to enable the
terminal count output (pin TC). The TC output thus enabled will produce a HIGH output
pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be
used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by tPHL
(propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula:
.
2.
Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Synchronous reset
Synchronous counting and loading
Two count enable inputs for n-bit cascading
Positive edge-triggered clock
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
74LVC163
Presettable synchronous 4-bit binary counter; synchronous
reset
Rev. 6 — 20 November 2012
Product data sheet
f
max
1
t
PHL max
t
su
+
-----------------------------------
=
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相关代理商/技术参数 |
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|---|---|
| 74LVC163DB-T | 功能描述:计数器 IC 3.3V SYNC 4-BIT BIN COUNTER RoHS:否 制造商:NXP Semiconductors 计数器类型:Binary Counters 逻辑系列:74LV 位数:10 计数法: 计数顺序: 工作电源电压:1 V to 5.5 V 工作温度范围:- 40 C to + 125 C 封装 / 箱体:SOT-109 封装:Reel |
| 74LVC163D-T | 功能描述:计数器 IC 3.3V SYNC 4-BIT BIN COUNTER RoHS:否 制造商:NXP Semiconductors 计数器类型:Binary Counters 逻辑系列:74LV 位数:10 计数法: 计数顺序: 工作电源电压:1 V to 5.5 V 工作温度范围:- 40 C to + 125 C 封装 / 箱体:SOT-109 封装:Reel |
| 74LVC163PW | 功能描述:计数器 IC 3.3V SYNC 4-BIT BIN COUNTER RoHS:否 制造商:NXP Semiconductors 计数器类型:Binary Counters 逻辑系列:74LV 位数:10 计数法: 计数顺序: 工作电源电压:1 V to 5.5 V 工作温度范围:- 40 C to + 125 C 封装 / 箱体:SOT-109 封装:Reel |
| 74LVC163PW,112 | 功能描述:计数器 IC 3.3V SYNC 4-BIT BIN RoHS:否 制造商:NXP Semiconductors 计数器类型:Binary Counters 逻辑系列:74LV 位数:10 计数法: 计数顺序: 工作电源电压:1 V to 5.5 V 工作温度范围:- 40 C to + 125 C 封装 / 箱体:SOT-109 封装:Reel |
| 74LVC163PW,118 | 功能描述:计数器 IC 4-BIT SYNC BIN CNTR RoHS:否 制造商:NXP Semiconductors 计数器类型:Binary Counters 逻辑系列:74LV 位数:10 计数法: 计数顺序: 工作电源电压:1 V to 5.5 V 工作温度范围:- 40 C to + 125 C 封装 / 箱体:SOT-109 封装:Reel |
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